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aiot
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efDataStatistics
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calculationOfAlarmUnprocessedData
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functionDefinition.h

functionDefinition.h 6.5 KB
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  1. /* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
    2. 

  2.  *
    3. 

  3.  * This program is free software; you can redistribute it and/or modify
    4. 

  4.  * it under the terms of the GNU General Public License version 2 and
    5. 

  5.  * only version 2 as published by the Free Software Foundation.
    6. 

  6.  *
    7. 

  7.  * This program is distributed in the hope that it will be useful,
    8. 

  8.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    9. 

  9.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    10. 

  10.  * GNU General Public License for more details.
    11. 

  11.  */
    12. 

  12. 

  13. #ifndef __ASM_ARCH_MSM_IRQS_8960_H
    14. 

  14. #define __ASM_ARCH_MSM_IRQS_8960_H
    15. 

  15. 

  16. /* MSM ACPU Interrupt Numbers */
    17. 

  17. 

  18. /* 0-15:  STI/SGI (software triggered/generated interrupts)
    19. 

  19.    16-31: PPI (private peripheral interrupts)
    20. 

  20.    32+:   SPI (shared peripheral interrupts) */
    21. 

  21. 

  22. #define GIC_PPI_START 16
    23. 

  23. #define GIC_SPI_START 32
    24. 

  24. 

  25. #define INT_VGIC				(GIC_PPI_START + 0)
    26. 

  26. #define INT_DEBUG_TIMER_EXP			(GIC_PPI_START + 1)
    27. 

  27. #define INT_GP_TIMER_EXP			(GIC_PPI_START + 2)
    28. 

  28. #define INT_GP_TIMER2_EXP			(GIC_PPI_START + 3)
    29. 

  29. #define WDT0_ACCSCSSNBARK_INT			(GIC_PPI_START + 4)
    30. 

  30. #define WDT1_ACCSCSSNBARK_INT			(GIC_PPI_START + 5)
    31. 

  31. #define AVS_SVICINT				(GIC_PPI_START + 6)
    32. 

  32. #define AVS_SVICINTSWDONE			(GIC_PPI_START + 7)
    33. 

  33. #define CPU_DBGCPUXCOMMRXFULL			(GIC_PPI_START + 8)
    34. 

  34. #define CPU_DBGCPUXCOMMTXEMPTY			(GIC_PPI_START + 9)
    35. 

  35. #define CPU_SICCPUXPERFMONIRPTREQ		(GIC_PPI_START + 10)
    36. 

  36. #define SC_AVSCPUXDOWN				(GIC_PPI_START + 11)
    37. 

  37. #define SC_AVSCPUXUP				(GIC_PPI_START + 12)
    38. 

  38. #define SC_SICCPUXACGIRPTREQ			(GIC_PPI_START + 13)
    39. 

  39. #define SC_SICCPUXEXTFAULTIRPTREQ		(GIC_PPI_START + 14)
    40. 

  40. /* PPI 15 is unused */
    41. 

  41. 

  42. #define SC_SICMPUIRPTREQ			(GIC_SPI_START + 0)
    43. 

  43. #define SC_SICL2IRPTREQ				(GIC_SPI_START + 1)
    44. 

  44. #define SC_SICL2PERFMONIRPTREQ			(GIC_SPI_START + 2)
    45. 

  45. #define SC_SICAGCIRPTREQ			(GIC_SPI_START + 3)
    46. 

  46. #define TLMM_APCC_DIR_CONN_IRQ_0		(GIC_SPI_START + 4)
    47. 

  47. #define TLMM_APCC_DIR_CONN_IRQ_1		(GIC_SPI_START + 5)
    48. 

  48. #define TLMM_APCC_DIR_CONN_IRQ_2		(GIC_SPI_START + 6)
    49. 

  49. #define TLMM_APCC_DIR_CONN_IRQ_3		(GIC_SPI_START + 7)
    50. 

  50. #define TLMM_APCC_DIR_CONN_IRQ_4		(GIC_SPI_START + 8)
    51. 

  51. #define TLMM_APCC_DIR_CONN_IRQ_5		(GIC_SPI_START + 9)
    52. 

  52. #define TLMM_APCC_DIR_CONN_IRQ_6		(GIC_SPI_START + 10)
    53. 

  53. #define TLMM_APCC_DIR_CONN_IRQ_7		(GIC_SPI_START + 11)
    54. 

  54. #define TLMM_APCC_DIR_CONN_IRQ_8		(GIC_SPI_START + 12)
    55. 

  55. #define TLMM_APCC_DIR_CONN_IRQ_9		(GIC_SPI_START + 13)
    56. 

  56. #define PM8921_SEC_IRQ_103			(GIC_SPI_START + 14)
    57. 

  57. #define PM8018_SEC_IRQ_106			(GIC_SPI_START + 15)
    58. 

  58. #define TLMM_APCC_SUMMARY_IRQ			(GIC_SPI_START + 16)
    59. 

  59. #define SPDM_RT_1_IRQ				(GIC_SPI_START + 17)
    60. 

  60. #define SPDM_DIAG_IRQ				(GIC_SPI_START + 18)
    61. 

  61. #define RPM_APCC_CPU0_GP_HIGH_IRQ		(GIC_SPI_START + 19)
    62. 

  62. #define RPM_APCC_CPU0_GP_MEDIUM_IRQ		(GIC_SPI_START + 20)
    63. 

  63. #define RPM_APCC_CPU0_GP_LOW_IRQ		(GIC_SPI_START + 21)
    64. 

  64. #define RPM_APCC_CPU0_WAKE_UP_IRQ		(GIC_SPI_START + 22)
    65. 

  65. #define RPM_APCC_CPU1_GP_HIGH_IRQ		(GIC_SPI_START + 23)
    66. 

  66. #define RPM_APCC_CPU1_GP_MEDIUM_IRQ		(GIC_SPI_START + 24)
    67. 

  67. #define RPM_APCC_CPU1_GP_LOW_IRQ		(GIC_SPI_START + 25)
    68. 

  68. #define RPM_APCC_CPU1_WAKE_UP_IRQ		(GIC_SPI_START + 26)
    69. 

  69. #define SSBI2_2_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 27)
    70. 

  70. #define SSBI2_2_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 28)
    71. 

  71. #define SSBI2_1_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 29)
    72. 

  72. #define SSBI2_1_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 30)
    73. 

  73. #define MSMC_SC_SEC_CE_IRQ			(GIC_SPI_START + 31)
    74. 

  74. #define MSMC_SC_PRI_CE_IRQ			(GIC_SPI_START + 32)
    75. 

  75. #define SLIMBUS0_CORE_EE1_IRQ			(GIC_SPI_START + 33)
    76. 

  76. #define SLIMBUS0_BAM_EE1_IRQ			(GIC_SPI_START + 34)
    77. 

  77. #define Q6FW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 35)
    78. 

  78. #define Q6SW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 36)
    79. 

  79. #define MSS_TO_APPS_IRQ_0			(GIC_SPI_START + 37)
    80. 

  80. #define MSS_TO_APPS_IRQ_1			(GIC_SPI_START + 38)
    81. 

  81. #define MSS_TO_APPS_IRQ_2			(GIC_SPI_START + 39)
    82. 

  82. #define MSS_TO_APPS_IRQ_3			(GIC_SPI_START + 40)
    83. 

  83. #define MSS_TO_APPS_IRQ_4			(GIC_SPI_START + 41)
    84. 

  84. #define MSS_TO_APPS_IRQ_5			(GIC_SPI_START + 42)
    85. 

  85. #define MSS_TO_APPS_IRQ_6			(GIC_SPI_START + 43)
    86. 

  86. #define MSS_TO_APPS_IRQ_7			(GIC_SPI_START + 44)
    87. 

  87. #define MSS_TO_APPS_IRQ_8			(GIC_SPI_START + 45)
    88. 

  88. #define MSS_TO_APPS_IRQ_9			(GIC_SPI_START + 46)
    89. 

  89. #define VPE_IRQ					(GIC_SPI_START + 47)
    90. 

  90. #define VFE_IRQ					(GIC_SPI_START + 48)
    91. 

  91. #define VCODEC_IRQ				(GIC_SPI_START + 49)
    92. 

  92. #define TV_ENC_IRQ				(GIC_SPI_START + 50)
    93. 

  93. #define SMMU_VPE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 51)
    94. 

  94. #define SMMU_VPE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 52)
    95. 

  95. #define SMMU_VFE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 53)
    96. 

  96. #define SMMU_VFE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 54)
    97. 

  97. #define SMMU_VCODEC_B_CB_SC_SECURE_IRQ		(GIC_SPI_START + 55)
    98. 

  98. #define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 56)
    99. 

  99. #define SMMU_VCODEC_A_CB_SC_SECURE_IRQ		(GIC_SPI_START + 57)
    100. 

  100. #define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 58)
    101. 

  101. #define SMMU_ROT_CB_SC_SECURE_IRQ		(GIC_SPI_START + 59)
    102. 

  102. #define SMMU_ROT_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 60)
    103. 

  103. #define SMMU_MDP1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 61)
    104. 

  104. #define SMMU_MDP1_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 62)
    105. 

  105. #define SMMU_MDP0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 63)
    106. 

  106. #define SMMU_MDP0_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 64)
    107. 

  107. #define SMMU_JPEGD_CB_SC_SECURE_IRQ		(GIC_SPI_START + 65)
    108. 

  108. #define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 66)
    109. 

  109. #define SMMU_IJPEG_CB_SC_SECURE_IRQ		(GIC_SPI_START + 67)
    110. 

  110. #define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 68)
    111. 

  111. #define SMMU_GFX3D_CB_SC_SECURE_IRQ		(GIC_SPI_START + 69)
    112. 

  112. #define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 70)
    113. 

  113. #define SMMU_GFX2D0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 71)
    114. 

  114. #define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 72)
    115. 

  115. #define ROT_IRQ					(GIC_SPI_START + 73)
    116. 

  116. #define MMSS_FABRIC_IRQ				(GIC_SPI_START + 74)
    117. 

  117. #define MDP_IRQ					(GIC_SPI_START + 75)
    118. 

  118. #define JPEGD_IRQ				(GIC_SPI_START + 76)
    119. 

  119. #define JPEG_IRQ				(GIC_SPI_START + 77)
    120. 

  120. #define MMSS_IMEM_IRQ				(GIC_SPI_START + 78)
    121. 

  121. #define HDMI_IRQ				(GIC_SPI_START + 79)
    122. 

  122. #define GFX3D_IRQ				(GIC_SPI_START + 80)
    123. 

  123. #define GFX2D0_IRQ				(GIC_SPI_START + 81)
    124. 

  124. #define DSI1_IRQ				(GIC_SPI_START + 82)
    125. 

  125. #define CSI_1_IRQ				(GIC_SPI_START + 83)
    126. 

  126. #define CSI_0_IRQ				(GIC_SPI_START + 84)
    127. 

  127. #define LPASS_SCSS_AUDIO_IF_OUT0_IRQ		(GIC_SPI_START + 85)
    128. 

  128. #define LPASS_SCSS_MIDI_IRQ			(GIC_SPI_START + 86)
    129. 

  129. #define LPASS_Q6SS_WDOG_EXPIRED			(GIC_SPI_START + 87)
    130. 

  130. #define LPASS_SCSS_GP_LOW_IRQ			(GIC_SPI_START + 88)
    131. 

  131. #define LPASS_SCSS_GP_MEDIUM_IRQ		(GIC_SPI_START + 89)
    132. 

  132. #define LPASS_SCSS_GP_HIGH_IRQ			(GIC_SPI_START + 90)
    133. 

  133. #define TOP_IMEM_IRQ				(GIC_SPI_START + 91)
    134. 

  134. #define FABRIC_SYS_IRQ				(GIC_SPI_START + 92)
    135. 

  135. #define FABRIC_APPS_IRQ				(GIC_SPI_START + 93)
    136. 

  136. #define USB1_HS_BAM_IRQ				(GIC_SPI_START + 94)
    137. 

  137. #define SDC4_BAM_IRQ				(GIC_SPI_START + 95)
    138. 

  138. #define SDC3_BAM_IRQ				(GIC_SPI_START + 96)
    139.