aiot/efDataDiscreteRateMining/averageCalculation/calculationOfAverageLeakageCurrent.h

#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H

/*
 * OMAP3430 Clock Management register bits
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2008 Nokia Corporation
 *
 * Written by Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* Bits shared between registers */

/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
#define OMAP3430ES2_EN_MMC3_MASK			(1 << 30)
#define OMAP3430ES2_EN_MMC3_SHIFT			30
#define OMAP3430_EN_MSPRO_MASK				(1 << 23)
#define OMAP3430_EN_MSPRO_SHIFT				23
#define OMAP3430_EN_HDQ_MASK				(1 << 22)
#define OMAP3430_EN_HDQ_SHIFT				22
#define OMAP3430ES1_EN_FSHOSTUSB_MASK			(1 << 5)
#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT			5
#define OMAP3430ES1_EN_D2D_MASK				(1 << 3)
#define OMAP3430ES1_EN_D2D_SHIFT			3
#define OMAP3430_EN_SSI_MASK				(1 << 0)
#define OMAP3430_EN_SSI_SHIFT				0

/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
#define OMAP3430ES2_EN_USBTLL_SHIFT			2
#define OMAP3430ES2_EN_USBTLL_MASK			(1 << 2)

/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
#define OMAP3430_EN_WDT2_MASK				(1 << 5)
#define OMAP3430_EN_WDT2_SHIFT				5

/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
#define OMAP3430_EN_CAM_MASK				(1 << 0)
#define OMAP3430_EN_CAM_SHIFT				0

/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
#define OMAP3430_EN_WDT3_MASK				(1 << 12)
#define OMAP3430_EN_WDT3_SHIFT				12

/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
#define OMAP3430_OVERRIDE_ENABLE_MASK			(1 << 19)


/* Bits specific to each register */

/* CM_FCLKEN_IVA2 */
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK		(1 << 0)
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT		0

/* CM_CLKEN_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT		8
#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK		(0x3 << 8)
#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT		4
#define OMAP3430_IVA2_DPLL_FREQSEL_MASK			(0xf << 4)
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT		3
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK		(1 << 3)
#define OMAP3430_EN_IVA2_DPLL_SHIFT			0
#define OMAP3430_EN_IVA2_DPLL_MASK			(0x7 << 0)

/* CM_IDLEST_IVA2 */
#define OMAP3430_ST_IVA2_SHIFT				0
#define OMAP3430_ST_IVA2_MASK				(1 << 0)

/* CM_IDLEST_PLL_IVA2 */
#define OMAP3430_ST_IVA2_CLK_SHIFT			0
#define OMAP3430_ST_IVA2_CLK_MASK			(1 << 0)

/* CM_AUTOIDLE_PLL_IVA2 */
#define OMAP3430_AUTO_IVA2_DPLL_SHIFT			0
#define OMAP3430_AUTO_IVA2_DPLL_MASK			(0x7 << 0)

/* CM_CLKSEL1_PLL_IVA2 */
#define OMAP3430_IVA2_CLK_SRC_SHIFT			19
#define OMAP3430_IVA2_CLK_SRC_MASK			(0x7 << 19)
#define OMAP3430_IVA2_CLK_SRC_WIDTH			3
#define OMAP3430_IVA2_DPLL_MULT_SHIFT			8
#define OMAP3430_IVA2_DPLL_MULT_MASK			(0x7ff << 8)
#define OMAP3430_IVA2_DPLL_DIV_SHIFT			0
#define OMAP3430_IVA2_DPLL_DIV_MASK			(0x7f << 0)

/* CM_CLKSEL2_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT		0
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH		5

/* CM_CLKSTCTRL_IVA2 */
#define OMAP3430_CLKTRCTRL_IVA2_SHIFT			0
#define OMAP3430_CLKTRCTRL_IVA2_MASK			(0x3 << 0)

/* CM_CLKSTST_IVA2 */
#define OMAP3430_CLKACTIVITY_IVA2_SHIFT			0
#define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)

/* CM_REVISION specific bits */

/* CM_SYSCONFIG specific bits */

/* CM_CLKEN_PLL_MPU */
#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT		8
#define OMAP3430_MPU_DPLL_RAMPTIME_MASK			(0x3 << 8)
#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT			4
#define OMAP3430_MPU_DPLL_FREQSEL_MASK			(0xf << 4)
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT		3
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK		(1 << 3)
#define OMAP3430_EN_MPU_DPLL_SHIFT			0
#define OMAP3430_EN_MPU_DPLL_MASK			(0x7 << 0)

/* CM_IDLEST_MPU */
#define OMAP3430_ST_MPU_MASK				(1 << 0)

/* CM_IDLEST_PLL_MPU */
#define OMAP3430_ST_MPU_CLK_SHIFT			0
#define OMAP3430_ST_MPU_CLK_MASK			(1 << 0)
#define OMAP3430_ST_MPU_CLK_WIDTH			1

/* CM_AUTOIDLE_PLL_MPU */
#define OMAP3430_AUTO_MPU_DPLL_SHIFT			0
#define OMAP3430_AUTO_MPU_DPLL_MASK			(0x7 << 0)

/* CM_CLKSEL1_PLL_MPU */
#define OMAP3430_MPU_CLK_SRC_SHIFT			19
#define OMAP3430_MPU_CLK_SRC_MASK			(0x7 << 19)
#define OMAP3430_MPU_CLK_SRC_WIDTH			3
#define OMAP3430_MPU_DPLL_MULT_SHIFT			8
#define OMAP3430_MPU_DPLL_MULT_MASK			(0x7ff << 8)
#define OMAP3430_MPU_DPLL_DIV_SHIFT			0
#define OMAP3430_MPU_DPLL_DIV_MASK			(0x7f << 0)

/* CM_CLKSEL2_PLL_MPU */
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT		0
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH		5

/* CM_CLKSTCTRL_MPU */
#define OMAP3430_CLKTRCTRL_MPU_SHIFT			0
#define OMAP3430_CLKTRCTRL_MPU_MASK			(0x3 << 0)

/* CM_CLKSTST_MPU */
#define OMAP3430_CLKACTIVITY_MPU_SHIFT			0
#define OMAP3430_CLKACTIVITY_MPU_MASK			(1 << 0)

/* CM_FCLKEN1_CORE specific bits */
#define OMAP3430_EN_MODEM_MASK				(1 << 31)
#define OMAP3430_EN_MODEM_SHIFT				31

/* CM_ICLKEN1_CORE specific bits */
#define OMAP3430_EN_ICR_MASK				(1 << 29)
#define OMAP3430_EN_ICR_SHIFT				29
#define OMAP3430_EN_AES2_MASK				(1 << 28)
#define OMAP3430_EN_AES2_SHIFT				28
#define OMAP3430_EN_SHA12_MASK				(1 << 27)
#define OMAP3430_EN_SHA12_SHIFT				27
#define OMAP3430_EN_DES2_MASK				(1 << 26)
#define OMAP3430_EN_DES2_SHIFT				26
#define OMAP3430ES1_EN_FAC_MASK				(1 << 8)
#define OMAP3430ES1_EN_FAC_SHIFT			8
#define OMAP3430_EN_MAILBOXES_MASK			(1 << 7)
#define OMAP3430_EN_MAILBOXES_SHIFT			7
#define OMAP3430_EN_OMAPCTRL_MASK			(1 << 6)
#define OMAP3430_EN_OMAPCTRL_SHIFT			6
#define OMAP3430_EN_SAD2D_MASK				(1 << 3)
#define OMAP3430_EN_SAD2D_SHIFT				3
#define OMAP3430_EN_SDRC_MASK				(1 << 1)
#define OMAP3430_EN_SDRC_SHIFT				1

/* AM35XX specific CM_ICLKEN1_CORE bits */
#define AM35XX_EN_IPSS_MASK				(1 << 4)
#define AM35XX_EN_IPSS_SHIFT				4

/* CM_ICLKEN2_CORE */
#define OMAP3430_EN_PKA_MASK				(1 << 4)
#define OMAP3430_EN_PKA_SHIFT				4
#define OMAP3430_EN_AES1_MASK				(1 << 3)
#define OMAP3430_EN_AES1_SHIFT				3
#define OMAP3430_EN_RNG_MASK				(1 << 2)
#define OMAP3430_EN_RNG_SHIFT				2
#define OMAP3430_EN_SHA11_MASK				(1 << 1)
#define OMAP3430_EN_SHA11_SHIFT				1
#define OMAP3430_EN_DES1_MASK				(1 << 0)
#define OMAP3430_EN_DES1_SHIFT				0

/* CM_ICLKEN3_CORE */
#define OMAP3430_EN_MAD2D_SHIFT				3
#define OMAP3430_EN_MAD2D_MASK				(1 << 3)

/* CM_FCLKEN3_CORE specific bits */
#define OMAP3430ES2_EN_TS_SHIFT				1
#define OMAP3430ES2_EN_TS_MASK				(1 << 1)
#define OMAP3430ES2_EN_CPEFUSE_SHIFT			0
#define OMAP3430ES2_EN_CPEFUSE_MASK			(1 << 0)

/* CM_IDLEST1_CORE specific bits */
#define OMAP3430ES2_ST_MMC3_SHIFT			30
#define OMAP3430ES2_ST_MMC3_MASK			(1 << 30)
#define OMAP3430_ST_ICR_SHIFT				29
#define OMAP3430_ST_ICR_MASK				(1 << 29)
#define OMAP3430_ST_AES2_SHIFT				28
#define OMAP3430_ST_AES2_MASK				(1 << 28)
#define OMAP3430_ST_SHA12_SHIFT				27
#define OMAP3430_ST_SHA12_MASK				(1 << 27)
#define OMAP3430_ST_DES2_SHIFT				26
#define OMAP3430_ST_DES2_MASK				(1 << 26)
#define OMAP3430_ST_MSPRO_SHIFT				23
#define OMAP3430_ST_MSPRO_MASK				(1 << 23)
#define AM35XX_ST_UART4_SHIFT				23
#define AM35XX_ST_UART4_MASK				(1 << 23)
#define OMAP3430_ST_HDQ_SHIFT				22
#define OMAP3430_ST_HDQ_MASK				(1 << 22)
#define OMAP3430ES1_ST_FAC_SHIFT			8
#define OMAP3430ES1_ST_FAC_MASK				(1 << 8)
#define OMAP3430ES2_ST_SSI_IDLE_SHIFT			8
#define OMAP3430ES2_ST_SSI_IDLE_MASK			(1 << 8)
#define OMAP3430_ST_MAILBOXES_SHIFT			7
#define OMAP3430_ST_MAILBOXES_MASK			(1 << 7)
#define OMAP3430_ST_OMAPCTRL_SHIFT			6
#define OMAP3430_ST_OMAPCTRL_MASK			(1 << 6)
#define OMAP3430_ST_SAD2D_SHIFT				3
#define OMAP3430_ST_SAD2D_MASK				(1 << 3)
#define OMAP3430_ST_SDMA_SHIFT				2
#define OMAP3430_ST_SDMA_MASK				(1 << 2)
#define OMAP3430_ST_SDRC_SHIFT				1
#define OMAP3430_ST_SDRC_MASK				(1 << 1)
#define OMAP3430_ST_SSI_STDBY_SHIFT			0
#define OMAP3430_ST_SSI_STDBY_MASK			(1 << 0)

/* AM35xx specific CM_IDLEST1_CORE bits */
#define AM35XX_ST_IPSS_SHIFT				5
#define AM35XX_ST_IPSS_MASK 				(1 << 5)

/* CM_IDLEST2_CORE */
#define OMAP3430_ST_PKA_SHIFT				4
#define OMAP3430_ST_PKA_MASK				(1 << 4)
#define OMAP3430_ST_AES1_SHIFT				3
#define OMAP3430_ST_AES1_MASK				(1 << 3)
#define OMAP3430_ST_RNG_SHIFT				2
#define OMAP3430_ST_RNG_MASK				(1 << 2)
#define OMAP3430_ST_SHA11_SHIFT				1
#define OMAP3430_ST_SHA11_MASK				(1 << 1)
#define OMAP3430_ST_DES1_SHIFT				0
#define OMAP3430_ST_DES1_MASK				(1 << 0)

/* CM_IDLEST3_CORE */
#define OMAP3430ES2_ST_USBTLL_SHIFT			2
#define OMAP3430ES2_ST_USBTLL_MASK			(1 << 2)
#define OMAP3430ES2_ST_CPEFUSE_SHIFT			0
#define OMAP3430ES2_ST_CPEFUSE_MASK			(1 << 0)

/* CM_AUTOIDLE1_CORE */
#define OMAP3430_AUTO_MODEM_MASK			(1 << 31)
#define OMAP3430_AUTO_MODEM_SHIFT			31
#define OMAP3430ES2_AUTO_MMC3_MASK			(1 << 30)
#define OMAP3430ES2_AUTO_MMC3_SHIFT			30
#define OMAP3430ES2_AUTO_ICR_MASK			(1 << 29)
#define OMAP3430ES2_AUTO_ICR_SHIFT			29
#define OMAP3430_AUTO_AES2_MASK				(1 << 28)
#define OMAP3430_AUTO_AES2_SHIFT			28
#define OMAP3430_AUTO_SHA12_MASK			(1 << 27)
#define OMAP3430_AUTO_SHA12_SHIFT			27
#define OMAP3430_AUTO_DES2_MASK				(1 << 26)
#define OMAP3430_AUTO_DES2_SHIFT			26
#define OMAP3430_AUTO_MMC2_MASK				(1 << 25)
#define OMAP3430_AUTO_MMC2_SHIFT			25
#define OMAP3430_AUTO_MMC1_MASK				(1 << 24)
#define OMAP3430_AUTO_MMC1_SHIFT			24
#define OMAP3430_AUTO_MSPRO_MASK			(1 << 23)
#define OMAP3430_AUTO_MSPRO_SHIFT			23
#define OMAP3430_AUTO_HDQ_MASK				(1 << 22)
#define OMAP3430_AUTO_HDQ_SHIFT				22
#define OMAP3430_AUTO_MCSPI4_MASK			(1 << 21)
#define OMAP3430_AUTO_MCSPI4_SHIFT			21