temperatureStandardDeviation.c 2.4 KB

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  1. /*
  2. * linux/arch/arm/mach-sa1100/jornada720.c
  3. *
  4. * HP Jornada720 init code
  5. *
  6. * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
  7. * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
  8. * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. */
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/tty.h>
  18. #include <linux/delay.h>
  19. #include <linux/platform_data/sa11x0-serial.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/ioport.h>
  22. #include <linux/mtd/mtd.h>
  23. #include <linux/mtd/partitions.h>
  24. #include <video/s1d13xxxfb.h>
  25. #include <asm/hardware/sa1111.h>
  26. #include <asm/page.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/setup.h>
  29. #include <asm/mach/arch.h>
  30. #include <asm/mach/flash.h>
  31. #include <asm/mach/map.h>
  32. #include <mach/hardware.h>
  33. #include <mach/irqs.h>
  34. #include "generic.h"
  35. /*
  36. * HP Documentation referred in this file:
  37. * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
  38. */
  39. /* line 110 of HP's doc */
  40. #define TUCR_VAL 0x20000400
  41. /* memory space (line 52 of HP's doc) */
  42. #define SA1111REGSTART 0x40000000
  43. #define SA1111REGLEN 0x00002000
  44. #define EPSONREGSTART 0x48000000
  45. #define EPSONREGLEN 0x00100000
  46. #define EPSONFBSTART 0x48200000
  47. /* 512kB framebuffer */
  48. #define EPSONFBLEN 512*1024
  49. static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
  50. /* line 344 of HP's doc */
  51. {0x0001,0x00}, // Miscellaneous Register
  52. {0x01FC,0x00}, // Display Mode Register
  53. {0x0004,0x00}, // General IO Pins Configuration Register 0
  54. {0x0005,0x00}, // General IO Pins Configuration Register 1
  55. {0x0008,0x00}, // General IO Pins Control Register 0
  56. {0x0009,0x00}, // General IO Pins Control Register 1
  57. {0x0010,0x01}, // Memory Clock Configuration Register
  58. {0x0014,0x11}, // LCD Pixel Clock Configuration Register
  59. {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
  60. {0x001C,0x01}, // MediaPlug Clock Configuration Register
  61. {0x001E,0x01}, // CPU To Memory Wait State Select Register
  62. {0x0020,0x00}, // Memory Configuration Register
  63. {0x0021,0x45}, // DRAM Refresh Rate Register
  64. {0x002A,0x01}, // DRAM Timings Control Register 0
  65. {0x002B,0x03}, // DRAM Timings Control Register 1
  66. {0x0030,0x1c}, // Panel Type Register
  67. {0x0031,0x00}, // MOD Rate Register