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cablePowerDataOperation.h

cablePowerDataOperation.h 5.5 KB
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  1. #ifndef __ASM_ARCH_PXA3xx_U2D_H
    2. 

  2. #define __ASM_ARCH_PXA3xx_U2D_H
    3. 

  3. 

  4. #include <mach/bitfield.h>
    5. 

  5. 

  6. /*
    7. 

  7.  * USB2 device controller registers and bits definitions
    8. 

  8.  */
    9. 

  9. #define U2DCR		(0x0000)	/* U2D Control Register */
    10. 

  10. #define U2DCR_NDC	(1   << 31)	/* NAK During Config */
    11. 

  11. #define U2DCR_HSTC	(0x7 << 28)	/* High Speed Timeout Calibration */
    12. 

  12. #define U2DCR_SPEOREN	(1   << 27)	/* Short Packet EOR INTR generation Enable */
    13. 

  13. #define U2DCR_FSTC	(0x7 << 24)	/* Full Speed Timeout Calibration */
    14. 

  14. #define U2DCR_UCLKOVR	(1   << 22)	/* UTM Clock Override */
    15. 

  15. #define U2DCR_ABP	(1   << 21)	/* Application Bus Power */
    16. 

  16. #define U2DCR_ADD	(1   << 20)	/* Application Device Disconnect */
    17. 

  17. #define U2DCR_CC	(1   << 19)	/* Configuration Change */
    18. 

  18. #define U2DCR_HS	(1   << 18)	/* High Speed USB Detection */
    19. 

  19. #define U2DCR_SMAC	(1   << 17)	/* Switch Endpoint Memory to Active Configuration */
    20. 

  20. #define U2DCR_DWRE	(1   << 16)	/* Device Remote Wake-up Feature */
    21. 

  21. #define U2DCR_ACN	(0xf << 12)	/* Active U2D Configuration Number */
    22. 

  22. #define U2DCR_AIN	(0xf << 8)	/* Active U2D Interface Number */
    23. 

  23. #define U2DCR_AAISN	(0xf << 4)	/* Active U2D Alternate Interface Setting Number */
    24. 

  24. #define U2DCR_EMCE	(1   << 3)	/* Endpoint Memory Configuration Error */
    25. 

  25. #define U2DCR_UDR	(1   << 2)	/* U2D Resume */
    26. 

  26. #define U2DCR_UDA	(1   << 1)	/* U2D Active */
    27. 

  27. #define U2DCR_UDE	(1   << 0)	/* U2D Enable */
    28. 

  28. 

  29. #define U2DICR			(0x0004)	/* U2D Interrupt Control Register */
    30. 

  30. #define U2DISR			(0x000C)	/* U2D Interrupt Status Register */
    31. 

  31. #define U2DINT_CC		(1 << 31)	/* Interrupt - Configuration Change */
    32. 

  32. #define U2DINT_SOF		(1 << 30)	/* Interrupt - SOF */
    33. 

  33. #define U2DINT_USOF		(1 << 29)	/* Interrupt - micro SOF */
    34. 

  34. #define U2DINT_RU		(1 << 28)	/* Interrupt - Resume */
    35. 

  35. #define U2DINT_SU		(1 << 27)	/* Interrupt - Suspend */
    36. 

  36. #define U2DINT_RS		(1 << 26)	/* Interrupt - Reset */
    37. 

  37. #define U2DINT_DPE		(1 << 25)	/* Interrupt - Data Packet Error */
    38. 

  38. #define U2DINT_FIFOERR		(0x4)		/* Interrupt - endpoint FIFO error */
    39. 

  39. #define U2DINT_PACKETCMP	(0x2)		/* Interrupt - endpoint packet complete */
    40. 

  40. #define U2DINT_SPACKETCMP	(0x1)		/* Interrupt - endpoint short packet complete */
    41. 

  41. 

  42. #define U2DFNR			(0x0014)	/* U2D Frame Number Register */
    43. 

  43. 

  44. #define U2DINT(n, intr)		(((intr) & 0x07) << (((n) & 0x07) * 3))
    45. 

  45. #define U2DICR2			(0x0008)	/* U2D Interrupt Control Register 2 */
    46. 

  46. #define U2DISR2			(0x0010)	/* U2D Interrupt Status Register 2 */
    47. 

  47. 

  48. #define U2DOTGCR		(0x0020)	/* U2D OTG Control Register */
    49. 

  49. #define U2DOTGCR_OTGEN		(1 << 31)	/* On-The-Go Enable */
    50. 

  50. #define U2DOTGCR_AALTHNP	(1 << 30)	/* A-device Alternate Host Negotiation Protocal Port Support */
    51. 

  51. #define U2DOTGCR_AHNP		(1 << 29)	/* A-device Host Negotiation Protocal Support */
    52. 

  52. #define U2DOTGCR_BHNP		(1 << 28)	/* B-device Host Negotiation Protocal Enable */
    53. 

  53. 

  54. #ifdef CONFIG_CPU_PXA930
    55. 

  55. #define U2DOTGCR_LPA		(1 << 15)	/* ULPI low power mode active */
    56. 

  56. #define U2DOTGCR_IESI		(1 << 13)	/* OTG interrupt Enable */
    57. 

  57. #define U2DOTGCR_ISSI		(1 << 12)	/* OTG interrupt status */
    58. 

  58. #endif
    59. 

  59. 

  60. #define U2DOTGCR_CKAF	(1 << 5)	/* Carkit Mode Alternate Function Select */
    61. 

  61. #define U2DOTGCR_UTMID	(1 << 4)	/* UTMI Interface Disable */
    62. 

  62. #define U2DOTGCR_ULAF	(1 << 3)	/* ULPI Mode Alternate Function Select */
    63. 

  63. #define U2DOTGCR_SMAF	(1 << 2)	/* Serial Mode Alternate Function Select */
    64. 

  64. #define U2DOTGCR_RTSM	(1 << 1)	/* Return to Synchronous Mode (ULPI Mode) */
    65. 

  65. #define U2DOTGCR_ULE	(1 << 0)	/* ULPI Wrapper Enable */
    66. 

  66. 

  67. #define U2DOTGICR	(0x0024)	/* U2D OTG Interrupt Control Register */
    68. 

  68. #define U2DOTGISR	(0x0028)	/* U2D OTG Interrupt Status Register */
    69. 

  69. 

  70. #define U2DOTGINT_SF	(1 << 17)	/* OTG Set Feature Command Received */
    71. 

  71. #define U2DOTGINT_SI	(1 << 16)	/* OTG Interrupt */
    72. 

  72. #define U2DOTGINT_RLS1	(1 << 14)	/* RXCMD Linestate[1] Change Interrupt Rise */
    73. 

  73. #define U2DOTGINT_RLS0	(1 << 13)	/* RXCMD Linestate[0] Change Interrupt Rise */
    74. 

  74. #define U2DOTGINT_RID	(1 << 12)	/* RXCMD OTG ID Change Interrupt Rise */
    75. 

  75. #define U2DOTGINT_RSE	(1 << 11)	/* RXCMD OTG Session End Interrupt Rise */
    76. 

  76. #define U2DOTGINT_RSV	(1 << 10)	/* RXCMD OTG Session Valid Interrupt Rise */
    77. 

  77. #define U2DOTGINT_RVV	(1 << 9)	/* RXCMD OTG Vbus Valid Interrupt Rise */
    78. 

  78. #define U2DOTGINT_RCK	(1 << 8)	/* RXCMD Carkit Interrupt Rise */
    79. 

  79. #define U2DOTGINT_FLS1	(1 << 6)	/* RXCMD Linestate[1] Change Interrupt Fall */
    80. 

  80. #define U2DOTGINT_FLS0	(1 << 5)	/* RXCMD Linestate[0] Change Interrupt Fall */
    81. 

  81. #define U2DOTGINT_FID	(1 << 4)	/* RXCMD OTG ID Change Interrupt Fall */
    82. 

  82. #define U2DOTGINT_FSE	(1 << 3)	/* RXCMD OTG Session End Interrupt Fall */
    83. 

  83. #define U2DOTGINT_FSV	(1 << 2)	/* RXCMD OTG Session Valid Interrupt Fall */
    84. 

  84. #define U2DOTGINT_FVV	(1 << 1)	/* RXCMD OTG Vbus Valid Interrupt Fall */
    85. 

  85. #define U2DOTGINT_FCK	(1 << 0)	/* RXCMD Carkit Interrupt Fall */
    86. 

  86. 

  87. #define U2DOTGUSR	(0x002C)	/* U2D OTG ULPI Status Register */
    88. 

  88. #define U2DOTGUSR_LPA	(1 << 31)	/* ULPI Low Power Mode Active */
    89. 

  89. #define U2DOTGUSR_S6A	(1 << 30)	/* ULPI Serial Mode (6-pin) Active */
    90. 

  90. #define U2DOTGUSR_S3A	(1 << 29)	/* ULPI Serial Mode (3-pin) Active */
    91. 

  91. #define U2DOTGUSR_CKA	(1 << 28)	/* ULPI Car Kit Mode Active */
    92. 

  92. #define U2DOTGUSR_LS1	(1 << 6)	/* RXCMD Linestate 1 Status */
    93. 

  93. #define U2DOTGUSR_LS0	(1 << 5)	/* RXCMD Linestate 0 Status */
    94. 

  94. #define U2DOTGUSR_ID	(1 << 4)	/* OTG IDGnd Status */
    95. 

  95. #define U2DOTGUSR_SE	(1 << 3)	/* OTG Session End Status */
    96. 

  96. #define U2DOTGUSR_SV	(1 << 2)	/* OTG Session Valid Status */
    97. 

  97. #define U2DOTGUSR_VV	(1 << 1)	/* OTG Vbus Valid Status */
    98. 

  98. #define U2DOTGUSR_CK	(1 << 0)	/* Carkit Interrupt Status */
    99. 

  99. 

  100. #define U2DOTGUCR	(0x0030)	/* U2D OTG ULPI Control Register */
    101. 

  101. #define U2DOTGUCR_RUN	(1    << 25)	/* RUN */
    102. 

  102. #define U2DOTGUCR_RNW	(1    << 24)	/* Read or Write operation */
    103. 

  103. #define U2DOTGUCR_ADDR	(0x3f << 16)	/* Address of the ULPI PHY register */
    104.