#ifndef __ALPHA_T2__H__ #define __ALPHA_T2__H__ /* Fit everything into one 128MB HAE window. */ #define T2_ONE_HAE_WINDOW 1 #include #include #include /* * T2 is the internal name for the core logic chipset which provides * memory controller and PCI access for the SABLE-based systems. * * This file is based on: * * SABLE I/O Specification * Revision/Update Information: 1.3 * * jestabro@amt.tay1.dec.com Initial Version. * */ #define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */ /* GAMMA-SABLE is a SABLE with EV5-based CPUs */ /* All LYNX machines, EV4 or EV5, use the GAMMA bias also */ #define _GAMMA_BIAS 0x8000000000UL #if defined(CONFIG_ALPHA_GENERIC) #define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias #elif defined(CONFIG_ALPHA_GAMMA) #define GAMMA_BIAS _GAMMA_BIAS #else #define GAMMA_BIAS 0 #endif /* * Memory spaces: */ #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL) #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL) #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL) #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL) #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL) #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL) #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL) #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL) #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL) #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL) #define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL) #define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL) #define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL) #define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL) #define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL) #define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL) #define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL) #define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL) #define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL) #define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL) #define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL) #define T2_IVR (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL) #define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL) #define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL) /* The CSRs below are T3/T4 only */ #define T2_WBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL) #define T2_WMASK3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL) #define T2_TBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL) #define T2_TDR0 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL) #define T2_TDR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL) #define T2_TDR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL) #define T2_TDR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL) #define T2_TDR4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL) #define T2_TDR5 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL) #define T2_TDR6 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL) #define T2_TDR7 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL) #define T2_WBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL) #define T2_WMASK4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL) #define T2_TBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL) #define T2_AIR (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL) #define T2_VAR (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL) #define T2_DIR (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL) #define T2_ICE (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL) #ifndef T2_ONE_HAE_WINDOW #define T2_HAE_ADDRESS T2_HAE_1 #endif /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to 3.8fff.ffff * * +--------------+ 3 8000 0000 * | CPU 0 CSRs | * +--------------+ 3 8100 0000 * | CPU 1 CSRs | * +--------------+ 3 8200 0000 * | CPU 2 CSRs | * +--------------+ 3 8300 0000 * | CPU 3 CSRs | * +--------------+ 3 8400 0000 * | CPU Reserved | * +--------------+ 3 8700 0000 * | Mem Reserved | * +--------------+ 3 8800 0000 * | Mem 0 CSRs | * +--------------+ 3 8900 0000 * | Mem 1 CSRs | * +--------------+ 3 8a00 0000 * | Mem 2 CSRs | * +--------------+ 3 8b00 0000 * | Mem 3 CSRs | * +--------------+ 3 8c00 0000 * | Mem Reserved | * +--------------+ 3 8e00 0000 * | PCI Bridge | * +--------------+ 3 8f00 0000 * | Expansion IO | * +--------------+ 3 9000 0000