/* * SA-1101.h * * Copyright (c) Peter Danielsson 1999 * * Definition of constants related to the sa1101 * support chip for the sa1100 * */ /* Be sure that virtual mapping is defined right */ #ifndef __ASM_ARCH_HARDWARE_H #error You must include hardware.h not SA-1101.h #endif #ifndef SA1101_BASE #error You must define SA-1101 physical base address #endif #ifndef LANGUAGE # ifdef __ASSEMBLY__ # define LANGUAGE Assembly # else # define LANGUAGE C # endif #endif /* * We have mapped the sa1101 depending on the value of SA1101_BASE. * It then appears from 0xf4000000. */ #define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000) #define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE) #ifndef SA1101_p2v #define SA1101_p2v(PhAdd) (PhAdd) #endif #include #define C 0 #define Assembly 1 /* * Memory map */ #define __SHMEM_CONTROL0 0x00000000 #define __SYSTEM_CONTROL1 0x00000400 #define __ARBITER 0x00020000 #define __SYSTEM_CONTROL2 0x00040000 #define __SYSTEM_CONTROL3 0x00060000 #define __PARALLEL_PORT 0x00080000 #define __VIDMEM_CONTROL 0x00100000 #define __UPDATE_FIFO 0x00120000 #define __SHMEM_CONTROL1 0x00140000 #define __INTERRUPT_CONTROL 0x00160000 #define __USB_CONTROL 0x00180000 #define __TRACK_INTERFACE 0x001a0000 #define __MOUSE_INTERFACE 0x001b0000 #define __KEYPAD_INTERFACE 0x001c0000 #define __PCMCIA_INTERFACE 0x001e0000 #define __VGA_CONTROL 0x00200000 #define __GPIO_INTERFACE 0x00300000 /* * Macro that calculates real address for registers in the SA-1101 */ #define _SA1101( x ) ((x) + SA1101_BASE) /* * Interface and shared memory controller registers * * Registers * SKCR SA-1101 control register (read/write) * SMCR Shared Memory Controller Register * SNPR Snoop Register */ #define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */ #define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */ #define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */ #if LANGUAGE == C #define SKCR (*((volatile Word *) SA1101_p2v (_SKCR))) #define SMCR (*((volatile Word *) SA1101_p2v (_SMCR))) #define SNPR (*((volatile Word *) SA1101_p2v (_SNPR))) #define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */ #define SKCR_BCLKEn 0x0002 /* Enables BCLK */ #define SKCR_Sleep 0x0004 /* Sleep Mode */ #define SKCR_IRefEn 0x0008 /* DAC Iref input enable */ #define SKCR_VCOON 0x0010 /* VCO bias */ #define SKCR_ScanTestEn 0x0020 /* Enables scan test */ #define SKCR_ClockTestEn 0x0040 /* Enables clock test */ #define SMCR_DCAC Fld(2,0) /* Number of column address bits */ #define SMCR_DRAC Fld(2,2) /* Number of row address bits */ #define SMCR_ArbiterBias 0x0008 /* favor video or USB */ #define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */ #define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ (( (x) - 8 ) << FShft (SMCR_DCAC)) #define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ (( (x) - 9 ) << FShft (SMCR_DRAC)) #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ #define SNPR_WholeBank (1 << 23) /* Whole bank bit */ #define SNPR_BankSelect Fld(2,27) /* Bank select */ #define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */ #define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \ ( (x) << FShft (SNPR_VFBsize)) #define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \ (( (x) + 1 ) << FShft (SNPR_BankSelect )) #endif /* LANGUAGE == C */ /* * Video Memory Controller * * Registers * VMCCR Configuration register * VMCAR VMC address register * VMCDR VMC data register * */ #define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */ #define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */ #define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */ #if LANGUAGE == C #define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR))) #define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR))) #define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR))) #define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */ #define VMCCR_Config 0x0001 /* DRAM size */ #define VMCCR_RefPeriod Fld(2,3) /* Refresh period */ #define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */ #define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/ #define VMCCR_RefTest (1<<10) /* refresh test */ #define VMCCR_RefLow Fld(6,11) /* refresh low counter */ #define VMCCR_RefHigh Fld(7,17) /* refresh high counter */ #define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */ #define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */ #endif LANGUAGE == C /* Update FIFO * * Registers * UFCR Update FIFO Control Register * UFSR Update FIFO Status Register * UFLVLR update FIFO level register * UFDR update FIFO data register */ #define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */ #define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */ #define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */ #define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */ #if LANGUAGE == C #define UFCR (*((volatile Word *) SA1101_p2v (_UFCR))) #define UFSR (*((volatile Word *) SA1101_p2v (_UFSR))) #define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR))) #define UFDR (*((volatile Word *) SA1101_p2v (_UFDR))) #define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */ #define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */ #endif /* LANGUAGE == C */ /* System Controller * * Registers * SKPCR Power Control Register * SKCDR Clock Divider Register * DACDR1 DAC1 Data register * DACDR2 DAC2 Data register */ #define _SKPCR _SA1101(0x00000400) #define _SKCDR _SA1101(0x00040000) #define _DACDR1 _SA1101(0x00060000) #define _DACDR2 _SA1101(0x00060400) #if LANGUAGE == C #define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR))) #define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR))) #define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1))) #define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2))) #define SKPCR_UCLKEn 0x01 /* USB Enable */ #define SKPCR_PCLKEn 0x02 /* PS/2 Enable */ #define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */ #define SKPCR_VCLKEn 0x08 /* Video Controller Enable */ #define SKPCR_PICLKEn 0x10 /* parallel port Enable */ #define SKPCR_DCLKEn 0x20 /* DACs Enable */ #define SKPCR_nKPADEn 0x40 /* Multiplexer */ #define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */ #define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */ #define SKDCR_BCLKEn (1<<9) /* BCLK Divider */ #define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */ #define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */ #define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */ #define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */ #define SKDCR_ChargePump (1<<25) /* Charge pump control */ #define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */ #define SKDCR_ClkTestEn (1<<27) /* Test clock generator */ #define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */ #define DACDR_DACCount Fld(8,0) /* Count value */ #define DACDR1_DACCount DACDR_DACCount #define DACDR2_DACCount DACDR_DACCount #endif /* LANGUAGE == C */ /* * Parallel Port Interface * * Registers * IEEE_Config IEEE mode selection and programmable attributes * IEEE_Control Controls the states of IEEE port control outputs * IEEE_Data Forward transfer data register * IEEE_Addr Forward transfer address register * IEEE_Status Port IO signal status register * IEEE_IntStatus Port interrupts status register * IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels * IEEE_InitTime Forward timeout counter initial value * IEEE_TimerStatus Forward timeout counter current value * IEEE_FifoReset Reset forward transfer FIFO * IEEE_ReloadValue Counter reload value * IEEE_TestControl Control testmode * IEEE_TestDataIn Test data register * IEEE_TestDataInEn Enable test data * IEEE_TestCtrlIn Test control signals * IEEE_TestCtrlInEn Enable test control signals * IEEE_TestDataStat Current data bus value * */ /* * The control registers are defined as offsets from a base address */ #define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT ) #define _IEEE_Config _IEEE( 0x0000 ) #define _IEEE_Control _IEEE( 0x0400 ) #define _IEEE_Data _IEEE( 0x4000 ) #define _IEEE_Addr _IEEE( 0x0800 ) #define _IEEE_Status _IEEE( 0x0c00 ) #define _IEEE_IntStatus _IEEE( 0x1000 ) #define _IEEE_FifoLevels _IEEE( 0x1400 )