/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 07 MIPS Technologies, Inc. * Copyright (C) 2003, 2004 Maciej W. Rozycki */ #ifndef _ASM_MIPSREGS_H #define _ASM_MIPSREGS_H #include #include #include /* * The following macros are especially useful for __asm__ * inline assembler. */ #ifndef __STR #define __STR(x) #x #endif #ifndef STR #define STR(x) __STR(x) #endif /* * Configure language */ #ifdef __ASSEMBLY__ #define _ULCAST_ #else #define _ULCAST_ (unsigned long) #endif /* * Coprocessor 0 register names */ #define CP0_INDEX $0 #define CP0_RANDOM $1 #define CP0_ENTRYLO0 $2 #define CP0_ENTRYLO1 $3 #define CP0_CONF $3 #define CP0_CONTEXT $4 #define CP0_PAGEMASK $5 #define CP0_WIRED $6 #define CP0_INFO $7 #define CP0_BADVADDR $8 #define CP0_COUNT $9 #define CP0_ENTRYHI $10 #define CP0_COMPARE $11 #define CP0_STATUS $12 #define CP0_CAUSE $13 #define CP0_EPC $14 #define CP0_PRID $15 #define CP0_CONFIG $16 #define CP0_LLADDR $17 #define CP0_WATCHLO $18 #define CP0_WATCHHI $19 #define CP0_XCONTEXT $20 #define CP0_FRAMEMASK $21 #define CP0_DIAGNOSTIC $22 #define CP0_DEBUG $23 #define CP0_DEPC $24 #define CP0_PERFORMANCE $25 #define CP0_ECC $26 #define CP0_CACHEERR $27 #define CP0_TAGLO $28 #define CP0_TAGHI $29 #define CP0_ERROREPC $30 #define CP0_DESAVE $31 /* * R4640/R4650 cp0 register names. These registers are listed * here only for completeness; without MMU these CPUs are not useable * by Linux. A future ELKS port might take make Linux run on them * though ... */ #define CP0_IBASE $0 #define CP0_IBOUND $1 #define CP0_DBASE $2 #define CP0_DBOUND $3 #define CP0_CALG $17 #define CP0_IWATCH $18 #define CP0_DWATCH $19 /* * Coprocessor 0 Set 1 register names */ #define CP0_S1_DERRADDR0 $26 #define CP0_S1_DERRADDR1 $27 #define CP0_S1_INTCONTROL $20 /* * Coprocessor 0 Set 2 register names */ #define CP0_S2_SRSCTL $12 /* MIPSR2 */ /* * Coprocessor 0 Set 3 register names */ #define CP0_S3_SRSMAP $12 /* MIPSR2 */ /* * TX39 Series */ #define CP0_TX39_CACHE $7 /* * Coprocessor 1 (FPU) register names */ #define CP1_REVISION $0 #define CP1_STATUS $31 /* * FPU Status Register Values */ /* * Status Register Values */ #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ #define FPU_CSR_COND 0x00800000 /* $fcc0 */ #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ /* * Bits 18 - 20 of the FPU Status Register will be read as 0, * and should be written as zero. */ #define FPU_CSR_RSVD 0x001c0000 /* * X the exception cause indicator * E the exception enable * S the sticky/flag bit */ #define FPU_CSR_ALL_X 0x0003f000 #define FPU_CSR_UNI_X 0x00020000 #define FPU_CSR_INV_X 0x00010000 #define FPU_CSR_DIV_X 0x00008000 #define FPU_CSR_OVF_X 0x00004000 #define FPU_CSR_UDF_X 0x00002000 #define FPU_CSR_INE_X 0x00001000 #define FPU_CSR_ALL_E 0x00000f80 #define FPU_CSR_INV_E 0x00000800 #define FPU_CSR_DIV_E 0x00000400 #define FPU_CSR_OVF_E 0x00000200 #define FPU_CSR_UDF_E 0x00000100 #define FPU_CSR_INE_E 0x00000080 #define FPU_CSR_ALL_S 0x0000007c #define FPU_CSR_INV_S 0x00000040 #define FPU_CSR_DIV_S 0x00000020 #define FPU_CSR_OVF_S 0x00000010 #define FPU_CSR_UDF_S 0x00000008 #define FPU_CSR_INE_S 0x00000004 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ #define FPU_CSR_RM 0x00000003 #define FPU_CSR_RN 0x0 /* nearest */ #define FPU_CSR_RZ 0x1 /* towards zero */ #define FPU_CSR_RU 0x2 /* towards +Infinity */ #define FPU_CSR_RD 0x3 /* towards -Infinity */ /* * Values for PageMask register */ #ifdef CONFIG_CPU_VR41XX /* Why doesn't stupidity hurt ... */ #define PM_1K 0x00000000 #define PM_4K 0x00001800 #define PM_16K 0x00007800 #define PM_64K 0x0001f800 #define PM_256K 0x0007f800 #else #define PM_4K 0x00000000 #define PM_8K 0x00002000 #define PM_16K 0x00006000 #define PM_32K 0x0000e000 #define PM_64K 0x0001e000 #define PM_128K 0x0003e000 #define PM_256K 0x0007e000 #define PM_512K 0x000fe000 #define PM_1M 0x001fe000 #define PM_2M 0x003fe000 #define PM_4M 0x007fe000 #define PM_8M 0x00ffe000 #define PM_16M 0x01ffe000 #define PM_32M 0x03ffe000 #define PM_64M 0x07ffe000 #define PM_256M 0x1fffe000 #define PM_1G 0x7fffe000 #endif /* * Default page size for a given kernel configuration */ #ifdef CONFIG_PAGE_SIZE_4KB #define PM_DEFAULT_MASK PM_4K #elif defined(CONFIG_PAGE_SIZE_8KB) #define PM_DEFAULT_MASK PM_8K #elif defined(CONFIG_PAGE_SIZE_16KB) #define PM_DEFAULT_MASK PM_16K #elif defined(CONFIG_PAGE_SIZE_32KB) #define PM_DEFAULT_MASK PM_32K #elif defined(CONFIG_PAGE_SIZE_64KB) #define PM_DEFAULT_MASK PM_64K #else #error Bad page size configuration! #endif /* * Default huge tlb size for a given kernel configuration */ #ifdef CONFIG_PAGE_SIZE_4KB #define PM_HUGE_MASK PM_1M #elif defined(CONFIG_PAGE_SIZE_8KB) #define PM_HUGE_MASK PM_4M #elif defined(CONFIG_PAGE_SIZE_16KB) #define PM_HUGE_MASK PM_16M #elif defined(CONFIG_PAGE_SIZE_32KB) #define PM_HUGE_MASK PM_64M #elif defined(CONFIG_PAGE_SIZE_64KB) #define PM_HUGE_MASK PM_256M #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) #error Bad page size configuration for hugetlbfs! #endif /* * Values used for computation of new tlb entries */ #define PL_4K 12 #define PL_16K 14 #define PL_64K 16 #define PL_256K 18 #define PL_1M 20 #define PL_4M 22 #define PL_16M 24 #define PL_64M 26 #define PL_256M 28 /* * PageGrain bits */ #define PG_RIE (_ULCAST_(1) << 31) #define PG_XIE (_ULCAST_(1) << 30) #define PG_ELPA (_ULCAST_(1) << 29) #define PG_ESP (_ULCAST_(1) << 28) /* * R4x00 interrupt enable / cause bits */ #define IE_SW0 (_ULCAST_(1) << 8) #define IE_SW1 (_ULCAST_(1) << 9) #define IE_IRQ0 (_ULCAST_(1) << 10) #define IE_IRQ1 (_ULCAST_(1) << 11) #define IE_IRQ2 (_ULCAST_(1) << 12) #define IE_IRQ3 (_ULCAST_(1) << 13) #define IE_IRQ4 (_ULCAST_(1) << 14) #define IE_IRQ5 (_ULCAST_(1) << 15) /* * R4x00 interrupt cause bits */ #define C_SW0 (_ULCAST_(1) << 8) #define C_SW1 (_ULCAST_(1) << 9) #define C_IRQ0 (_ULCAST_(1) << 10) #define C_IRQ1 (_ULCAST_(1) << 11) #define C_IRQ2 (_ULCAST_(1) << 12) #define C_IRQ3 (_ULCAST_(1) << 13) #define C_IRQ4 (_ULCAST_(1) << 14) #define C_IRQ5 (_ULCAST_(1) << 15) /* * Bitfields in the R4xx0 cp0 status register */ #define ST0_IE 0x00000001 #define ST0_EXL 0x00000002 #define ST0_ERL 0x00000004 #define ST0_KSU 0x00000018 # define KSU_USER 0x00000010 # define KSU_SUPERVISOR 0x00000008 # define KSU_KERNEL 0x00000000 #define ST0_UX 0x00000020 #define ST0_SX 0x00000040