/* * System & MMR bit and Address definitions for ADSP-BF532 * * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF532_H #define _DEF_BF532_H /*********************************************************************************** */ /* System MMR Register Map */ /*********************************************************************************** */ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ #define CHIPID 0xFFC00014 /* Chip ID Register */ /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ #define SYSCR 0xFFC00104 /* System Configuration registe */ #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ #define RTC_STAT 0xFFC00300 /* RTC Status Register */ #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ /* UART Controller (0xFFC00400 - 0xFFC004FF) */ /* * Because include/linux/serial_reg.h have defined UART_*, * So we define blackfin uart regs to BFIN_UART_*. */ #define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ #define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ #define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ #define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ #define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ #define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ #if 0 #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ #endif #define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ #define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ #define SPI0_REGBASE 0xFFC00500 #define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */ #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ /* Asynchronous Memory Controller - External Bus Interface Unit */ #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ /* DMA Traffic controls */ #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ #define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ #define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ #define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ #define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ #define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ #define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ #define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ #define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ #define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ #define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ #define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ #define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ #define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ #define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ #define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ #define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ #define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ #define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ #define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ #define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ #define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ #define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ /*********************************************************************************** */ /* System MMR Register Bits */ /******************************************************************************* */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 #define CHIPID_MANUFACTURE 0x00000FFE /* SWRST Mask */ #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ /* SYSCR Masks */ #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ /* SIC_IAR0 Masks */ #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ /* SIC_IAR1 Masks */ #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ /* SIC_IAR2 Masks */ #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ /* SIC_IMASK Masks */ #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ /* SIC_IWR Masks */ #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ /* PPI_CONTROL Masks */ #define PORT_EN 0x00000001 /* PPI Port Enable */ #define PORT_DIR 0x00000002 /* PPI Port Direction */ #define XFR_TYPE 0x0000000C /* PPI Transfer Type */ #define PORT_CFG 0x00000030 /* PPI Port Configuration */ #define FLD_SEL 0x00000040 /* PPI Active Field Select */ #define PACK_EN 0x00000080 /* PPI Packing Mode */ #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ #define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ #define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ #define DLENGTH 0x00003800 /* PPI Data Length */ #define DLEN_8 0x0000 /* Data Length = 8 Bits */ #define DLEN_10 0x0800 /* Data Length = 10 Bits */ #define DLEN_11 0x1000 /* Data Length = 11 Bits */ #define DLEN_12 0x1800 /* Data Length = 12 Bits */ #define DLEN_13 0x2000 /* Data Length = 13 Bits */ #define DLEN_14 0x2800 /* Data Length = 14 Bits */ #define DLEN_15 0x3000 /* Data Length = 15 Bits */ #define DLEN_16 0x3800 /* Data Length = 16 Bits */ #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ #define POL 0x0000C000 /* PPI Signal Polarities */ #define POLC 0x4000 /* PPI Clock Polarity */ #define POLS 0x8000 /* PPI Frame Sync Polarity */ /* PPI_STATUS Masks */ #define FLD 0x00000400 /* Field Indicator */ #define FT_ERR 0x00000800 /* Frame Track Error */ #define OVR 0x00001000 /* FIFO Overflow Error */ #define UNDR 0x00002000 /* FIFO Underrun Error */ #define ERR_DET 0x00004000 /* Error Detected Indicator */