/* mb93493-regs.h: MB93493 companion chip registers * * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #ifndef _ASM_MB93493_REGS_H #define _ASM_MB93493_REGS_H #include #include #define __addr_MB93493(X) ((volatile unsigned long *)(__region_CS3 + (X))) #define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); }) #define __set_MB93493(X,V) \ do { \ *(volatile unsigned long *)(__region_CS3 + (X)) = (V); mb(); \ } while(0) #define __get_MB93493_STSR(X) __get_MB93493(0x3c0 + (X) * 4) #define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V)) #define MB93493_STSR_EN #define __addr_MB93493_IQSR(X) __addr_MB93493(0x3d0 + (X) * 4) #define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4) #define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V)) #define __get_MB93493_DQSR(X) __get_MB93493(0x3e0 + (X) * 4) #define __set_MB93493_DQSR(X,V) __set_MB93493(0x3e0 + (X) * 4, (V)) #define __get_MB93493_LBSER() __get_MB93493(0x3f0) #define __set_MB93493_LBSER(V) __set_MB93493(0x3f0, (V)) #define MB93493_LBSER_VDC 0x00010000 #define MB93493_LBSER_VCC 0x00020000 #define MB93493_LBSER_AUDIO 0x00040000 #define MB93493_LBSER_I2C_0 0x00080000 #define MB93493_LBSER_I2C_1 0x00100000 #define MB93493_LBSER_USB 0x00200000 #define MB93493_LBSER_GPIO 0x00800000 #define MB93493_LBSER_PCMCIA 0x01000000 #define __get_MB93493_LBSR() __get_MB93493(0x3fc) #define __set_MB93493_LBSR(V) __set_MB93493(0x3fc, (V)) /* * video display controller */ #define __get_MB93493_VDC(X) __get_MB93493(MB93493_VDC_##X) #define __set_MB93493_VDC(X,V) __set_MB93493(MB93493_VDC_##X, (V)) #define MB93493_VDC_RCURSOR 0x140 /* cursor position */ #define MB93493_VDC_RCT1 0x144 /* cursor colour 1 */ #define MB93493_VDC_RCT2 0x148 /* cursor colour 2 */ #define MB93493_VDC_RHDC 0x150 /* horizontal display period */ #define MB93493_VDC_RH_MARGINS 0x154 /* horizontal margin sizes */ #define MB93493_VDC_RVDC 0x158 /* vertical display period */ #define MB93493_VDC_RV_MARGINS 0x15c /* vertical margin sizes */ #define MB93493_VDC_RC 0x170 /* VDC control */ #define MB93493_VDC_RCLOCK 0x174 /* clock divider, DMA req delay */ #define MB93493_VDC_RBLACK 0x178 /* black insert sizes */ #define MB93493_VDC_RS 0x17c /* VDC status */ #define __addr_MB93493_VDC_BCI(X) ({ (volatile unsigned long *)(__region_CS3 + 0x000 + (X)); }) #define __addr_MB93493_VDC_TPO(X) (__region_CS3 + 0x1c0 + (X)) #define VDC_TPO_WIDTH 32 #define VDC_RC_DSR 0x00000080 /* VDC master reset */ #define VDC_RS_IT 0x00060000 /* interrupt indicators */ #define VDC_RS_IT_UNDERFLOW 0x00040000 /* - underflow event */ #define VDC_RS_IT_VSYNC 0x00020000 /* - VSYNC event */ #define VDC_RS_DFI 0x00010000 /* current interlace field number */ #define VDC_RS_DFI_TOP 0x00000000 /* - top field */ #define VDC_RS_DFI_BOTTOM 0x00010000 /* - bottom field */ #define VDC_RS_DCSR 0x00000010 /* cursor state */ #define VDC_RS_DCM 0x00000003 /* display mode */ #define VDC_RS_DCM_DISABLED 0x00000000 /* - display disabled */ #define VDC_RS_DCM_STOPPED 0x00000001 /* - VDC stopped */ #define VDC_RS_DCM_FREERUNNING 0x00000002 /* - VDC free-running */ #define VDC_RS_DCM_TRANSFERRING 0x00000003 /* - data being transferred to VDC */ /* * video capture controller */ #define __get_MB93493_VCC(X) __get_MB93493(MB93493_VCC_##X) #define __set_MB93493_VCC(X,V) __set_MB93493(MB93493_VCC_##X, (V)) #define MB93493_VCC_RREDUCT 0x104 /* reduction rate */ #define MB93493_VCC_RHY 0x108 /* horizontal brightness filter coefficients */ #define MB93493_VCC_RHC 0x10c /* horizontal colour-difference filter coefficients */ #define MB93493_VCC_RHSIZE 0x110 /* horizontal cycle sizes */ #define MB93493_VCC_RHBC 0x114 /* horizontal back porch size */ #define MB93493_VCC_RVCC 0x118 /* vertical capture period */ #define MB93493_VCC_RVBC 0x11c /* vertical back porch period */ #define MB93493_VCC_RV 0x120 /* vertical filter coefficients */ #define MB93493_VCC_RDTS 0x128 /* DMA transfer size */ #define MB93493_VCC_RDTS_4B 0x01000000 /* 4-byte transfer */ #define MB93493_VCC_RDTS_32B 0x03000000 /* 32-byte transfer */ #define MB93493_VCC_RDTS_SHIFT 24 #define MB93493_VCC_RCC 0x130 /* VCC control */ #define MB93493_VCC_RIS 0x134 /* VCC interrupt status */ #define __addr_MB93493_VCC_TPI(X) (__region_CS3 + 0x180 + (X)) #define VCC_RHSIZE_RHCC 0x000007ff #define VCC_RHSIZE_RHCC_SHIFT 0 #define VCC_RHSIZE_RHTCC 0x0fff0000 #define VCC_RHSIZE_RHTCC_SHIFT 16 #define VCC_RVBC_RVBC 0x00003f00 #define VCC_RVBC_RVBC_SHIFT 8 #define VCC_RREDUCT_RHR 0x07ff0000 #define VCC_RREDUCT_RHR_SHIFT 16 #define VCC_RREDUCT_RVR 0x000007ff #define VCC_RREDUCT_RVR_SHIFT 0 #define VCC_RCC_CE 0x00000001 /* VCC enable */ #define VCC_RCC_CS 0x00000002 /* request video capture start */ #define VCC_RCC_CPF 0x0000000c /* pixel format */ #define VCC_RCC_CPF_YCBCR_16 0x00000000 /* - YCbCr 4:2:2 16-bit format */ #define VCC_RCC_CPF_RGB 0x00000004 /* - RGB 4:4:4 format */ #define VCC_RCC_CPF_YCBCR_24 0x00000008 /* - YCbCr 4:2:2 24-bit format */ #define VCC_RCC_CPF_BT656 0x0000000c /* - ITU R-BT.656 format */ #define VCC_RCC_CPF_SHIFT 2 #define VCC_RCC_CSR 0x00000080 /* request reset */ #define VCC_RCC_HSIP 0x00000100 /* HSYNC polarity */ #define VCC_RCC_HSIP_LOACT 0x00000000 /* - low active */ #define VCC_RCC_HSIP_HIACT 0x00000100 /* - high active */ #define VCC_RCC_VSIP 0x00000200 /* VSYNC polarity */ #define VCC_RCC_VSIP_LOACT 0x00000000 /* - low active */ #define VCC_RCC_VSIP_HIACT 0x00000200 /* - high active */ #define VCC_RCC_CIE 0x00000800 /* interrupt enable */ #define VCC_RCC_CFP 0x00001000 /* RGB pixel packing */ #define VCC_RCC_CFP_4TO3 0x00000000 /* - pack 4 pixels into 3 words */ #define VCC_RCC_CFP_1TO1 0x00001000 /* - pack 1 pixel into 1 words */ #define VCC_RCC_CSM 0x00006000 /* interlace specification */ #define VCC_RCC_CSM_ONEPASS 0x00002000 /* - non-interlaced */ #define VCC_RCC_CSM_INTERLACE 0x00004000 /* - interlaced */ #define VCC_RCC_CSM_SHIFT 13 #define VCC_RCC_ES 0x00008000 /* capture start polarity */ #define VCC_RCC_ES_NEG 0x00000000 /* - negative edge */