/* * Support for the Arcom ZEUS. * * Copyright (C) 2006 Arcom Control Systems Ltd. * * Loosely based on Arcom's 2.6.16.28. * Maintained by Marc Zyngier * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "generic.h" /* * Interrupt handling */ static unsigned long zeus_irq_enabled_mask; static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, }; static const int zeus_isa_irq_map[] = { 0, /* ISA irq #0, invalid */ 0, /* ISA irq #1, invalid */ 0, /* ISA irq #2, invalid */ 1 << 0, /* ISA irq #3 */ 1 << 1, /* ISA irq #4 */ 1 << 2, /* ISA irq #5 */ 1 << 3, /* ISA irq #6 */ 1 << 4, /* ISA irq #7 */ 0, /* ISA irq #8, invalid */ 0, /* ISA irq #9, invalid */ 1 << 5, /* ISA irq #10 */ 1 << 6, /* ISA irq #11 */ 1 << 7, /* ISA irq #12 */ }; static inline int zeus_irq_to_bitmask(unsigned int irq) { return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)]; } static inline int zeus_bit_to_irq(int bit) { return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0); } static void zeus_ack_irq(struct irq_data *d) { __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ); } static void zeus_mask_irq(struct irq_data *d) { zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq)); } static void zeus_unmask_irq(struct irq_data *d) { zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq); } static inline unsigned long zeus_irq_pending(void) { return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask; } static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned long pending; pending = zeus_irq_pending(); do { /* we're in a chained irq handler, * so ack the interrupt by hand */ desc->irq_data.chip->irq_ack(&desc->irq_data); if (likely(pending)) { irq = zeus_bit_to_irq(__ffs(pending)); generic_handle_irq(irq); } pending = zeus_irq_pending(); } while (pending); } static struct irq_chip zeus_irq_chip = { .name = "ISA", .irq_ack = zeus_ack_irq, .irq_mask = zeus_mask_irq, .irq_unmask = zeus_unmask_irq, }; static void __init zeus_init_irq(void) { int level; int isa_irq; pxa27x_init_irq(); /* Peripheral IRQs. It would be nice to move those inside driver configuration, but it is not supported at the moment. */ irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); /* Setup ISA IRQs */ for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { isa_irq = zeus_bit_to_irq(level); irq_set_chip_and_handler(isa_irq, &zeus_irq_chip, handle_edge_irq); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); } irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); } /* * Platform devices */ /* Flash */ static struct resource zeus_mtd_resources[] = { [0] = { /* NOR Flash (up to 64MB) */ .start = ZEUS_FLASH_PHYS, .end = ZEUS_FLASH_PHYS + SZ_64M - 1, .flags = IORESOURCE_MEM, }, [1] = { /* SRAM */ .start = ZEUS_SRAM_PHYS, .end = ZEUS_SRAM_PHYS + SZ_512K - 1, .flags = IORESOURCE_MEM, }, }; static struct physmap_flash_data zeus_flash_data[] = { [0] = { .width = 2, .parts = NULL, .nr_parts = 0, }, }; static struct platform_device zeus_mtd_devices[] = { [0] = { .name = "physmap-flash", .id = 0, .dev = { .platform_data = &zeus_flash_data[0], }, .resource = &zeus_mtd_resources[0], .num_resources = 1, }, }; /* Serial */ static struct resource zeus_serial_resources[] = { { .start = 0x10000000, .end = 0x1000000f, .flags = IORESOURCE_MEM, }, { .start = 0x10800000, .end = 0x1080000f, .flags = IORESOURCE_MEM, }, { .start = 0x11000000, .end = 0x1100000f, .flags = IORESOURCE_MEM, }, { .start = 0x40100000, .end = 0x4010001f, .flags = IORESOURCE_MEM, }, { .start = 0x40200000, .end = 0x4020001f, .flags = IORESOURCE_MEM, }, { .start = 0x40700000, .end = 0x4070001f, .flags = IORESOURCE_MEM, }, }; static struct plat_serial8250_port serial_platform_data[] = { /* External UARTs */ /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */ { /* COM1 */ .mapbase = 0x10000000, .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1, .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, .iotype = UPIO_MEM, }, { /* COM2 */ .mapbase = 0x10800000, .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1, .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, .iotype = UPIO_MEM, }, { /* COM3 */ .mapbase = 0x11000000, .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1, .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, .iotype = UPIO_MEM, }, { /* COM4 */ .mapbase = 0x11800000, .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1, .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, .iotype = UPIO_MEM, }, /* Internal UARTs */ { /* FFUART */ .membase = (void *)&FFUART, .mapbase = __PREG(FFUART), .irq = IRQ_FFUART, .uartclk = 921600 * 16, .regshift = 2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, .iotype = UPIO_MEM, }, { /* BTUART */ .membase = (void *)&BTUART, .mapbase = __PREG(BTUART), .irq = IRQ_BTUART, .uartclk = 921600 * 16, .regshift = 2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, .iotype = UPIO_MEM, }, { /* STUART */ .membase = (void *)&STUART, .mapbase = __PREG(STUART), .irq = IRQ_STUART, .uartclk = 921600 * 16, .regshift = 2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, .iotype = UPIO_MEM, }, { }, }; static struct platform_device zeus_serial_device = { .name = "serial8250", .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, .num_resources = ARRAY_SIZE(zeus_serial_resources), .resource = zeus_serial_resources, }; /* Ethernet */ static struct resource zeus_dm9k0_resource[] = { [0] = { .start = ZEUS_ETH0_PHYS, .end = ZEUS_ETH0_PHYS + 1, .flags = IORESOURCE_MEM }, [1] = { .start = ZEUS_ETH0_PHYS + 2, .end = ZEUS_ETH0_PHYS + 3, .flags = IORESOURCE_MEM }, [2] = { .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO), .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; static struct resource zeus_dm9k1_resource[] = { [0] = { .start = ZEUS_ETH1_PHYS, .end = ZEUS_ETH1_PHYS + 1, .flags = IORESOURCE_MEM }, [1] = { .start = ZEUS_ETH1_PHYS + 2, .end = ZEUS_ETH1_PHYS + 3, .flags = IORESOURCE_MEM, }, [2] = { .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO), .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; static struct dm9000_plat_data zeus_dm9k_platdata = { .flags = DM9000_PLATF_16BITONLY, }; static struct platform_device zeus_dm9k0_device = { .name = "dm9000", .id = 0, .num_resources = ARRAY_SIZE(zeus_dm9k0_resource), .resource = zeus_dm9k0_resource, .dev = { .platform_data = &zeus_dm9k_platdata, } }; static struct platform_device zeus_dm9k1_device = { .name = "dm9000", .id = 1, .num_resources = ARRAY_SIZE(zeus_dm9k1_resource), .resource = zeus_dm9k1_resource, .dev = { .platform_data = &zeus_dm9k_platdata, } }; /* External SRAM */ static struct resource zeus_sram_resource = { .start = ZEUS_SRAM_PHYS, .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1, .flags = IORESOURCE_MEM, }; static struct platform_device zeus_sram_device = { .name = "pxa2xx-8bit-sram", .id = 0, .num_resources = 1, .resource = &zeus_sram_resource, }; /* SPI interface on SSP3 */ static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = { .num_chipselect = 1, .enable_dma = 1, }; /* CAN bus on SPI */ static int zeus_mcp2515_setup(struct spi_device *sdev) { int err; err = gpio_request(ZEUS_CAN_SHDN_GPIO, "CAN shutdown"); if (err) return err; err = gpio_direction_output(ZEUS_CAN_SHDN_GPIO, 1); if (err) { gpio_free(ZEUS_CAN_SHDN_GPIO); return err; } return 0; } static int zeus_mcp2515_transceiver_enable(int enable) { gpio_set_value(ZEUS_CAN_SHDN_GPIO, !enable); return 0; } static struct mcp251x_platform_data zeus_mcp2515_pdata = { .oscillator_frequency = 16*1000*1000, .board_specific_setup = zeus_mcp2515_setup, .power_enable = zeus_mcp2515_transceiver_enable, }; static struct spi_board_info zeus_spi_board_info[] = { [0] = { .modalias = "mcp2515", .platform_data = &zeus_mcp2515_pdata, .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO), .max_speed_hz = 1*1000*1000, .bus_num = 3, .mode = SPI_MODE_0, .chip_select = 0, }, }; /* Leds */ static struct gpio_led zeus_leds[] = { [0] = { .name = "zeus:yellow:1", .default_trigger = "heartbeat", .gpio = ZEUS_EXT0_GPIO(3), .active_low = 1, }, [1] = { .name = "zeus:yellow:2", .default_trigger = "default-on", .gpio = ZEUS_EXT0_GPIO(4), .active_low = 1, }, [2] = { .name = "zeus:yellow:3", .default_trigger = "default-on", .gpio = ZEUS_EXT0_GPIO(5), .active_low = 1, }, }; static struct gpio_led_platform_data zeus_leds_info = { .leds = zeus_leds, .num_leds = ARRAY_SIZE(zeus_leds), }; static struct platform_device zeus_leds_device = { .name = "leds-gpio", .id = -1, .dev = { .platform_data = &zeus_leds_info, }, }; static void zeus_cf_reset(int state) { u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL); if (state) cpld_state |= ZEUS_CPLD_CONTROL_CF_RST; else cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST; __raw_writew(cpld_state, ZEUS_CPLD_CONTROL); } static struct arcom_pcmcia_pdata zeus_pcmcia_info = { .cd_gpio = ZEUS_CF_CD_GPIO, .rdy_gpio = ZEUS_CF_RDY_GPIO, .pwr_gpio = ZEUS_CF_PWEN_GPIO, .reset = zeus_cf_reset, }; static struct platform_device zeus_pcmcia_device = { .name = "zeus-pcmcia", .id = -1, .dev = { .platform_data = &zeus_pcmcia_info, }, }; static struct resource zeus_max6369_resource = { .start = ZEUS_CPLD_EXTWDOG_PHYS, .end = ZEUS_CPLD_EXTWDOG_PHYS, .flags = IORESOURCE_MEM, }; struct platform_device zeus_max6369_device = { .name = "max6369_wdt", .id = -1, .resource = &zeus_max6369_resource, .num_resources = 1, }; static struct platform_device *zeus_devices[] __initdata = { &zeus_serial_device, &zeus_mtd_devices[0], &zeus_dm9k0_device, &zeus_dm9k1_device, &zeus_sram_device, &zeus_leds_device, &zeus_pcmcia_device, &zeus_max6369_device, }; /* AC'97 */ static pxa2xx_audio_ops_t zeus_ac97_info = { .reset_gpio = 95, }; /* * USB host */ static int zeus_ohci_init(struct device *dev) { int err; /* Switch on port 2. */ if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) { dev_err(dev, "Can't request USB2_PWREN\n"); return err; } if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) { gpio_free(ZEUS_USB2_PWREN_GPIO); dev_err(dev, "Can't enable USB2_PWREN\n"); return err; } /* Port 2 is shared between host and client interface. */ UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; return 0; } static void zeus_ohci_exit(struct device *dev) { /* Power-off port 2 */ gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0); gpio_free(ZEUS_USB2_PWREN_GPIO); } static struct pxaohci_platform_data zeus_ohci_platform_data = { .port_mode = PMM_NPS_MODE, /* Clear Power Control Polarity Low and set Power Sense * Polarity Low. Supply power to USB ports. */ .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW, .init = zeus_ohci_init, .exit = zeus_ohci_exit, }; /* * Flat Panel */ static void zeus_lcd_power(int on, struct fb_var_screeninfo *si) { gpio_set_value(ZEUS_LCD_EN_GPIO, on); } static void zeus_backlight_power(int on) { gpio_set_value(ZEUS_BKLEN_GPIO, on); } static int zeus_setup_fb_gpios(void) { int err; if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN"))) goto out_err; if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0))) goto out_err_lcd; if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN"))) goto out_err_lcd; if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0))) goto out_err_bkl; return 0; out_err_bkl: gpio_free(ZEUS_BKLEN_GPIO); out_err_lcd: gpio_free(ZEUS_LCD_EN_GPIO); out_err: return err; } static struct pxafb_mode_info zeus_fb_mode_info[] = { { .pixclock = 39722, .xres = 640, .yres = 480, .bpp = 16, .hsync_len = 63, .left_margin = 16, .right_margin = 81, .vsync_len = 2, .upper_margin = 12, .lower_margin = 31, .sync = 0, }, }; static struct pxafb_mach_info zeus_fb_info = { .modes = zeus_fb_mode_info, .num_modes = 1, .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, .pxafb_lcd_power = zeus_lcd_power, .pxafb_backlight_power = zeus_backlight_power,