/*
 * R8A7740 processor support
 *
 * Copyright (C) 2011  Renesas Solutions Corp.
 * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
#include <mach/intc.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

/*
 *		INTCA
 */
enum {
	UNUSED_INTCA = 0,

	/* interrupt sources INTCA */
	DIRC,
	ATAPI,
	IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
	AP_ARM_COMMTX, AP_ARM_COMMRX,
	MFI, MFIS,
	BBIF1, BBIF2,
	USBHSDMAC,
	USBF_OUL_SOF, USBF_IXL_INT,
	SGX540,
	CMT1_0, CMT1_1, CMT1_2, CMT1_3,
	CMT2,
	CMT3,
	KEYSC,
	SCIFA0, SCIFA1, SCIFA2, SCIFA3,
	MSIOF2, MSIOF1,
	SCIFA4, SCIFA5, SCIFB,
	FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
	SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
	AP_ARM_L2CINT,
	IRDA,
	TPU0,
	SCIFA6, SCIFA7,
	GbEther,
	ICBS0,
	DDM,
	SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
	RWDT0,
	DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
	DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
	DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
	DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
	DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
	DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
	SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
	HDMI,
	USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
	RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
	SPU2_0, SPU2_1,
	FSI, FMSI,
	HDMI_SSS, HDMI_KEY,
	IPMMU,
	AP_ARM_CTIIRQ, AP_ARM_PMURQ,
	MFIS2,
	CPORTR2S,
	CMT14, CMT15,
	MMCIF_0, MMCIF_1, MMCIF_2,
	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,

	/* interrupt groups INTCA */
	DMAC1_1, DMAC1_2,
	DMAC2_1, DMAC2_2,
	DMAC3_1, DMAC3_2,
	AP_ARM1, AP_ARM2,
	SDHI0, SDHI1, SDHI2,
	SHWYSTAT,
	USBF, USBH1, USBH2,
	RSPI, SPU2, FLCTL, IIC1,
};

static struct intc_vect intca_vectors[] __initdata = {
	INTC_VECT(DIRC,			0x0560),
	INTC_VECT(ATAPI,		0x05E0),
	INTC_VECT(IIC1_ALI,		0x0780),
	INTC_VECT(IIC1_TACKI,		0x07A0),
	INTC_VECT(IIC1_WAITI,		0x07C0),
	INTC_VECT(IIC1_DTEI,		0x07E0),
	INTC_VECT(AP_ARM_COMMTX,	0x0840),
	INTC_VECT(AP_ARM_COMMRX,	0x0860),
	INTC_VECT(MFI,			0x0900),
	INTC_VECT(MFIS,			0x0920),
	INTC_VECT(BBIF1,		0x0940),
	INTC_VECT(BBIF2,		0x0960),
	INTC_VECT(USBHSDMAC,		0x0A00),
	INTC_VECT(USBF_OUL_SOF,		0x0A20),
	INTC_VECT(USBF_IXL_INT,		0x0A40),
	INTC_VECT(SGX540,		0x0A60),
	INTC_VECT(CMT1_0,		0x0B00),
	INTC_VECT(CMT1_1,		0x0B20),
	INTC_VECT(CMT1_2,		0x0B40),
	INTC_VECT(CMT1_3,		0x0B60),
	INTC_VECT(CMT2,			0x0B80),
	INTC_VECT(CMT3,			0x0BA0),
	INTC_VECT(KEYSC,		0x0BE0),
	INTC_VECT(SCIFA0,		0x0C00),
	INTC_VECT(SCIFA1,		0x0C20),
	INTC_VECT(SCIFA2,		0x0C40),
	INTC_VECT(SCIFA3,		0x0C60),
	INTC_VECT(MSIOF2,		0x0C80),
	INTC_VECT(MSIOF1,		0x0D00),
	INTC_VECT(SCIFA4,		0x0D20),
	INTC_VECT(SCIFA5,		0x0D40),
	INTC_VECT(SCIFB,		0x0D60),
	INTC_VECT(FLCTL_FLSTEI,		0x0D80),
	INTC_VECT(FLCTL_FLTENDI,	0x0DA0),
	INTC_VECT(FLCTL_FLTREQ0I,	0x0DC0),
	INTC_VECT(FLCTL_FLTREQ1I,	0x0DE0),
	INTC_VECT(SDHI0_0,		0x0E00),
	INTC_VECT(SDHI0_1,		0x0E20),
	INTC_VECT(SDHI0_2,		0x0E40),
	INTC_VECT(SDHI0_3,		0x0E60),
	INTC_VECT(SDHI1_0,		0x0E80),
	INTC_VECT(SDHI1_1,		0x0EA0),
	INTC_VECT(SDHI1_2,		0x0EC0),
	INTC_VECT(SDHI1_3,		0x0EE0),
	INTC_VECT(AP_ARM_L2CINT,	0x0FA0),
	INTC_VECT(IRDA,			0x0480),
	INTC_VECT(TPU0,			0x04A0),
	INTC_VECT(SCIFA6,		0x04C0),
	INTC_VECT(SCIFA7,		0x04E0),
	INTC_VECT(GbEther,		0x0500),
	INTC_VECT(ICBS0,		0x0540),
	INTC_VECT(DDM,			0x1140),
	INTC_VECT(SDHI2_0,		0x1200),
	INTC_VECT(SDHI2_1,		0x1220),
	INTC_VECT(SDHI2_2,		0x1240),
	INTC_VECT(SDHI2_3,		0x1260),
	INTC_VECT(RWDT0,		0x1280),
	INTC_VECT(DMAC1_1_DEI0,		0x2000),
	INTC_VECT(DMAC1_1_DEI1,		0x2020),
	INTC_VECT(DMAC1_1_DEI2,		0x2040),
	INTC_VECT(DMAC1_1_DEI3,		0x2060),
	INTC_VECT(DMAC1_2_DEI4,		0x2080),
	INTC_VECT(DMAC1_2_DEI5,		0x20A0),
	INTC_VECT(DMAC1_2_DADERR,	0x20C0),
	INTC_VECT(DMAC2_1_DEI0,		0x2100),
	INTC_VECT(DMAC2_1_DEI1,		0x2120),
	INTC_VECT(DMAC2_1_DEI2,		0x2140),
	INTC_VECT(DMAC2_1_DEI3,		0x2160),
	INTC_VECT(DMAC2_2_DEI4,		0x2180),
	INTC_VECT(DMAC2_2_DEI5,		0x21A0),
	INTC_VECT(DMAC2_2_DADERR,	0x21C0),
	INTC_VECT(DMAC3_1_DEI0,		0x2200),
	INTC_VECT(DMAC3_1_DEI1,		0x2220),
	INTC_VECT(DMAC3_1_DEI2,		0x2240),
	INTC_VECT(DMAC3_1_DEI3,		0x2260),
	INTC_VECT(DMAC3_2_DEI4,		0x2280),
	INTC_VECT(DMAC3_2_DEI5,		0x22A0),
	INTC_VECT(DMAC3_2_DADERR,	0x22C0),
	INTC_VECT(SHWYSTAT_RT,		0x1300),
	INTC_VECT(SHWYSTAT_HS,		0x1320),
	INTC_VECT(SHWYSTAT_COM,		0x1340),
	INTC_VECT(USBH_INT,		0x1540),
	INTC_VECT(USBH_OHCI,		0x1560),
	INTC_VECT(USBH_EHCI,		0x1580),
	INTC_VECT(USBH_PME,		0x15A0),
	INTC_VECT(USBH_BIND,		0x15C0),
	INTC_VECT(HDMI,			0x1700),
	INTC_VECT(RSPI_OVRF,		0x1780),
	INTC_VECT(RSPI_SPTEF,		0x17A0),
	INTC_VECT(RSPI_SPRF,		0x17C0),
	INTC_VECT(SPU2_0,		0x1800),
	INTC_VECT(SPU2_1,		0x1820),
	INTC_VECT(FSI,			0x1840),
	INTC_VECT(FMSI,			0x1860),
	INTC_VECT(HDMI_SSS,		0x18A0),
	INTC_VECT(HDMI_KEY,		0x18C0),
	INTC_VECT(IPMMU,		0x1920),
	INTC_VECT(AP_ARM_CTIIRQ,	0x1980),
	INTC_VECT(AP_ARM_PMURQ,		0x19A0),
	INTC_VECT(MFIS2,		0x1A00),
	INTC_VECT(CPORTR2S,		0x1A20),
	INTC_VECT(CMT14,		0x1A40),
	INTC_VECT(CMT15,		0x1A60),
	INTC_VECT(MMCIF_0,		0x1AA0),
	INTC_VECT(MMCIF_1,		0x1AC0),
	INTC_VECT(MMCIF_2,		0x1AE0),
	INTC_VECT(SIM_ERI,		0x1C00),
	INTC_VECT(SIM_RXI,		0x1C20),
	INTC_VECT(SIM_TXI,		0x1C40),
	INTC_VECT(SIM_TEI,		0x1C60),
	INTC_VECT(STPRO_0,		0x1C80),
	INTC_VECT(STPRO_1,		0x1CA0),
	INTC_VECT(STPRO_2,		0x1CC0),
	INTC_VECT(STPRO_3,		0x1CE0),
	INTC_VECT(STPRO_4,		0x1D00),
};

static struct intc_group intca_groups[] __initdata = {
	INTC_GROUP(DMAC1_1,
		   DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
	INTC_GROUP(DMAC1_2,
		   DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
	INTC_GROUP(DMAC2_1,
		   DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
	INTC_GROUP(DMAC2_2,
		   DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
	INTC_GROUP(DMAC3_1,
		   DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
	INTC_GROUP(DMAC3_2,
		   DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
	INTC_GROUP(AP_ARM1,
		   AP_ARM_COMMTX, AP_ARM_COMMRX),
	INTC_GROUP(AP_ARM2,
		   AP_ARM_CTIIRQ, AP_ARM_PMURQ),
	INTC_GROUP(USBF,
		   USBF_OUL_SOF, USBF_IXL_INT),
	INTC_GROUP(SDHI0,
		   SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
	INTC_GROUP(SDHI1,
		   SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
	INTC_GROUP(SDHI2,
		   SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
	INTC_GROUP(SHWYSTAT,
		   SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
	INTC_GROUP(USBH1, /* FIXME */
		   USBH_INT, USBH_OHCI),
	INTC_GROUP(USBH2, /* FIXME */
		   USBH_EHCI,
		   USBH_PME, USBH_BIND),
	INTC_GROUP(RSPI,
		   RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
	INTC_GROUP(SPU2,
		   SPU2_0, SPU2_1),
	INTC_GROUP(FLCTL,
		   FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(IIC1,
		   IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
};

static struct intc_mask_reg intca_mask_registers[] __initdata = {
	{ /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
	  { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
	    0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
	{ /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
	  { ATAPI, 0, DIRC, 0,
	    DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
	{ /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
	  { 0, 0, 0, 0,
	    BBIF1, BBIF2, MFIS, MFI } },
	{ /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
	  { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
	    DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
	{ /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
	  { DDM, 0, 0, 0,
	    0, 0, 0, 0 } },
	{ /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
	  { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
	    SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
	{ /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
	  { SCIFB, SCIFA5, SCIFA4, MSIOF1,
	    0, 0, MSIOF2, 0 } },
	{ /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
	  { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
	{ /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
	  { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
	    0, USBHSDMAC, 0, AP_ARM_L2CINT } },