/*
 * Copyright 2005-2010 Analog Devices Inc.
 *
 * Licensed under the Clear BSD license or the GPL-2 (or later)
 */

#ifndef _DEF_BF534_H
#define _DEF_BF534_H

/************************************************************************************
** System MMR Register Map
*************************************************************************************/
/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
#define PLL_CTL				0xFFC00000	/* PLL Control Register                                         */
#define PLL_DIV				0xFFC00004	/* PLL Divide Register                                          */
#define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register           */
#define PLL_STAT			0xFFC0000C	/* PLL Status Register                                          */
#define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register                                      */
#define CHIPID				0xFFC00014      /* Chip ID Register                                             */

/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
#define SWRST				0xFFC00100	/* Software Reset Register                                      */
#define SYSCR				0xFFC00104	/* System Configuration Register                        */
#define SIC_RVECT			0xFFC00108	/* Interrupt Reset Vector Address Register      */
#define SIC_IMASK			0xFFC0010C	/* Interrupt Mask Register                                      */
#define SIC_IAR0			0xFFC00110	/* Interrupt Assignment Register 0                      */
#define SIC_IAR1			0xFFC00114	/* Interrupt Assignment Register 1                      */
#define SIC_IAR2			0xFFC00118	/* Interrupt Assignment Register 2                      */
#define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3                      */
#define SIC_ISR				0xFFC00120	/* Interrupt Status Register                            */
#define SIC_IWR				0xFFC00124	/* Interrupt Wakeup Register                            */