#ifndef _IOP13XX_HW_H_ #define _IOP13XX_HW_H_ #ifndef __ASSEMBLY__ /* The ATU offsets can change based on the strapping */ extern u32 iop13xx_atux_pmmr_offset; extern u32 iop13xx_atue_pmmr_offset; void iop13xx_init_early(void); void iop13xx_init_irq(void); void iop13xx_map_io(void); void iop13xx_platform_init(void); void iop13xx_add_tpmi_devices(void); void iop13xx_init_irq(void); void iop13xx_restart(char, const char *); /* CPUID CP6 R0 Page 0 */ static inline int iop13xx_cpu_id(void) { int id; asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id)); return id; } /* WDTCR CP6 R7 Page 9 */ static inline u32 read_wdtcr(void) { u32 val; asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); return val; } static inline void write_wdtcr(u32 val) { asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); } /* WDTSR CP6 R8 Page 9 */ static inline u32 read_wdtsr(void) { u32 val; asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); return val; } static inline void write_wdtsr(u32 val) { asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); } /* RCSR - Reset Cause Status Register */ static inline u32 read_rcsr(void) { u32 val; asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); return val; } extern unsigned long get_iop_tick_rate(void); #endif /* * IOP13XX I/O and Mem space regions for PCI autoconfiguration */ #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */ #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE /* PCI MAP * bus range cpu phys cpu virt note * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window * * IO MAP * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window */ #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\ IOP13XX_PCIX_LOWER_MEM_BA) #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\ IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\ IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\ IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\ IOP13XX_PCIX_LOWER_MEM_BA) /* PCI-E ranges */ #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL #define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */ #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\ IOP13XX_PCIE_LOWER_MEM_BA) #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\ IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\ IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */ #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\ IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\ IOP13XX_PCIE_LOWER_MEM_BA) /* PBI Ranges */ #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\ IOP13XX_PBI_MEM_WINDOW_SIZE - 1) /* * IOP13XX chipset registers */ #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ #define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */ #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\ + IOP13XX_PMMR_PHYS_MEM_BASE) #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\ + IOP13XX_PMMR_VIRT_MEM_BASE) #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) #define IOP13XX_PMMR_SIZE 0x00080000 /*=================== Defines for Platform Devices =====================*/ #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300) #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340) #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300) #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340) #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540) #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500) #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520) #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540) /* ATU selection flags */ /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */ #define IOP13XX_INIT_ATU_DEFAULT (0) #define IOP13XX_INIT_ATU_ATUX (1 << 0) #define IOP13XX_INIT_ATU_ATUE (1 << 1) #define IOP13XX_INIT_ATU_NONE (1 << 2) /* UART selection flags */ /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */ #define IOP13XX_INIT_UART_DEFAULT (0) #define IOP13XX_INIT_UART_0 (1 << 0) #define IOP13XX_INIT_UART_1 (1 << 1) /* I2C selection flags */ /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */ #define IOP13XX_INIT_I2C_DEFAULT (0) #define IOP13XX_INIT_I2C_0 (1 << 0) #define IOP13XX_INIT_I2C_1 (1 << 1) #define IOP13XX_INIT_I2C_2 (1 << 2) /* ADMA selection flags */ /* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */ #define IOP13XX_INIT_ADMA_DEFAULT (0) #define IOP13XX_INIT_ADMA_0 (1 << 0) #define IOP13XX_INIT_ADMA_1 (1 << 1) #define IOP13XX_INIT_ADMA_2 (1 << 2) /* Platform devices */ #define IQ81340_NUM_UART 2 #define IQ81340_NUM_I2C 3 #define IQ81340_NUM_PHYS_MAP_FLASH 1 #define IQ81340_NUM_ADMA 3 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \ IQ81340_NUM_I2C + \ IQ81340_NUM_PHYS_MAP_FLASH + \ IQ81340_NUM_ADMA)