/* * R8A7740 processor support * * Copyright (C) 2011 Renesas Solutions Corp. * Copyright (C) 2011 Kuninori Morimoto * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of the * License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #define CPU_ALL_PORT(fn, pfx, sfx) \ PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \ PORT_10(fn, pfx##20, sfx), \ PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) enum { PINMUX_RESERVED = 0, /* PORT0_DATA -> PORT211_DATA */ PINMUX_DATA_BEGIN, PORT_ALL(DATA), PINMUX_DATA_END, /* PORT0_IN -> PORT211_IN */ PINMUX_INPUT_BEGIN, PORT_ALL(IN), PINMUX_INPUT_END, /* PORT0_IN_PU -> PORT211_IN_PU */ PINMUX_INPUT_PULLUP_BEGIN, PORT_ALL(IN_PU), PINMUX_INPUT_PULLUP_END, /* PORT0_IN_PD -> PORT211_IN_PD */ PINMUX_INPUT_PULLDOWN_BEGIN, PORT_ALL(IN_PD), PINMUX_INPUT_PULLDOWN_END, /* PORT0_OUT -> PORT211_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), PINMUX_OUTPUT_END, PINMUX_FUNCTION_BEGIN, PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */ PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */ PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */ PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */ PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */ PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */ PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */ PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */ PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */ PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */ MSEL1CR_31_0, MSEL1CR_31_1, MSEL1CR_30_0, MSEL1CR_30_1, MSEL1CR_29_0, MSEL1CR_29_1, MSEL1CR_28_0, MSEL1CR_28_1, MSEL1CR_27_0, MSEL1CR_27_1, MSEL1CR_26_0, MSEL1CR_26_1, MSEL1CR_16_0, MSEL1CR_16_1, MSEL1CR_15_0, MSEL1CR_15_1, MSEL1CR_14_0, MSEL1CR_14_1, MSEL1CR_13_0, MSEL1CR_13_1, MSEL1CR_12_0, MSEL1CR_12_1, MSEL1CR_9_0, MSEL1CR_9_1, MSEL1CR_7_0, MSEL1CR_7_1, MSEL1CR_6_0, MSEL1CR_6_1, MSEL1CR_5_0, MSEL1CR_5_1, MSEL1CR_4_0, MSEL1CR_4_1, MSEL1CR_3_0, MSEL1CR_3_1, MSEL1CR_2_0, MSEL1CR_2_1, MSEL1CR_0_0, MSEL1CR_0_1, MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */ MSEL3CR_6_0, MSEL3CR_6_1, MSEL4CR_19_0, MSEL4CR_19_1, MSEL4CR_18_0, MSEL4CR_18_1, MSEL4CR_15_0, MSEL4CR_15_1, MSEL4CR_10_0, MSEL4CR_10_1, MSEL4CR_6_0, MSEL4CR_6_1, MSEL4CR_4_0, MSEL4CR_4_1, MSEL4CR_1_0, MSEL4CR_1_1, MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */ MSEL5CR_30_0, MSEL5CR_30_1, MSEL5CR_29_0, MSEL5CR_29_1, MSEL5CR_27_0, MSEL5CR_27_1, MSEL5CR_25_0, MSEL5CR_25_1, MSEL5CR_23_0, MSEL5CR_23_1, MSEL5CR_21_0, MSEL5CR_21_1, MSEL5CR_19_0, MSEL5CR_19_1, MSEL5CR_17_0, MSEL5CR_17_1, MSEL5CR_15_0, MSEL5CR_15_1, MSEL5CR_14_0, MSEL5CR_14_1, MSEL5CR_13_0, MSEL5CR_13_1, MSEL5CR_12_0, MSEL5CR_12_1, MSEL5CR_11_0, MSEL5CR_11_1, MSEL5CR_10_0, MSEL5CR_10_1, MSEL5CR_8_0, MSEL5CR_8_1, MSEL5CR_7_0, MSEL5CR_7_1, MSEL5CR_6_0, MSEL5CR_6_1, MSEL5CR_5_0, MSEL5CR_5_1, MSEL5CR_4_0, MSEL5CR_4_1, MSEL5CR_3_0, MSEL5CR_3_1, MSEL5CR_2_0, MSEL5CR_2_1, MSEL5CR_0_0, MSEL5CR_0_1, PINMUX_FUNCTION_END, PINMUX_MARK_BEGIN, /* IRQ */ IRQ0_PORT2_MARK, IRQ0_PORT13_MARK, IRQ1_MARK, IRQ2_PORT11_MARK, IRQ2_PORT12_MARK, IRQ3_PORT10_MARK, IRQ3_PORT14_MARK, IRQ4_PORT15_MARK, IRQ4_PORT172_MARK, IRQ5_PORT0_MARK, IRQ5_PORT1_MARK, IRQ6_PORT121_MARK, IRQ6_PORT173_MARK, IRQ7_PORT120_MARK, IRQ7_PORT209_MARK, IRQ8_MARK, IRQ9_PORT118_MARK, IRQ9_PORT210_MARK, IRQ10_MARK, IRQ11_MARK, IRQ12_PORT42_MARK, IRQ12_PORT97_MARK, IRQ13_PORT64_MARK, IRQ13_PORT98_MARK, IRQ14_PORT63_MARK, IRQ14_PORT99_MARK, IRQ15_PORT62_MARK, IRQ15_PORT100_MARK, IRQ16_PORT68_MARK, IRQ16_PORT211_MARK, IRQ17_MARK, IRQ18_MARK, IRQ19_MARK, IRQ20_MARK, IRQ21_MARK, IRQ22_MARK, IRQ23_MARK, IRQ24_MARK, IRQ25_MARK, IRQ26_PORT58_MARK, IRQ26_PORT81_MARK, IRQ27_PORT57_MARK, IRQ27_PORT168_MARK, IRQ28_PORT56_MARK, IRQ28_PORT169_MARK, IRQ29_PORT50_MARK, IRQ29_PORT170_MARK, IRQ30_PORT49_MARK, IRQ30_PORT171_MARK, IRQ31_PORT41_MARK, IRQ31_PORT167_MARK, /* Function */ /* DBGT */ DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK, DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK, DBGMD21_MARK, /* FSI-A */ FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */ FSIAISLD_PORT5_MARK, FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */ FSIASPDIF_PORT18_MARK, FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK, FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK, FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK, /* FSI-B */ FSIBCK_MARK, /* FMSI */ FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */ FMSISLD_PORT6_MARK, FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK, FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK, FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK, /* SCIFA0 */ SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK, SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, /* SCIFA1 */ SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, SCIFA1_RTS_MARK, /* SCIFA2 */ SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */ SCIFA2_SCK_PORT199_MARK, SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, SCIFA2_CTS_MARK, SCIFA2_RTS_MARK, /* SCIFA3 */ SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */ SCIFA3_SCK_PORT116_MARK, SCIFA3_CTS_PORT117_MARK, SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK, SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */ SCIFA3_SCK_PORT158_MARK, SCIFA3_CTS_PORT162_MARK, SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK, /* SCIFA4 */ SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */ SCIFA4_TXD_PORT13_MARK, SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */ SCIFA4_TXD_PORT203_MARK,