/* * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2008 by Sascha Hauer * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * MA 02110-1301, USA. */ #ifndef __MACH_IOMUX_MX3_H__ #define __MACH_IOMUX_MX3_H__ #include /* * various IOMUX output functions */ #define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ #define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ #define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ #define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ #define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ #define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ #define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ #define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ #define IOMUX_ICONFIG_NONE 0 /* not configured for input */ #define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ #define IOMUX_ICONFIG_FUNC 2 /* used as function */ #define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ #define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ #define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) #define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) #define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) #define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) /* * various IOMUX pad functions */ enum iomux_pad_config { PAD_CTL_NOLOOPBACK = 0x0 << 9, PAD_CTL_LOOPBACK = 0x1 << 9, PAD_CTL_PKE_NONE = 0x0 << 8, PAD_CTL_PKE_ENABLE = 0x1 << 8, PAD_CTL_PUE_KEEPER = 0x0 << 7, PAD_CTL_PUE_PUD = 0x1 << 7, PAD_CTL_100K_PD = 0x0 << 5, PAD_CTL_100K_PU = 0x1 << 5, PAD_CTL_47K_PU = 0x2 << 5, PAD_CTL_22K_PU = 0x3 << 5, PAD_CTL_HYS_CMOS = 0x0 << 4, PAD_CTL_HYS_SCHMITZ = 0x1 << 4, PAD_CTL_ODE_CMOS = 0x0 << 3, PAD_CTL_ODE_OpenDrain = 0x1 << 3, PAD_CTL_DRV_NORMAL = 0x0 << 1, PAD_CTL_DRV_HIGH = 0x1 << 1, PAD_CTL_DRV_MAX = 0x2 << 1, PAD_CTL_SRE_SLOW = 0x0 << 0, PAD_CTL_SRE_FAST = 0x1 << 0 }; /* * various IOMUX general purpose functions */ enum iomux_gp_func { MUX_PGP_FIRI = 1 << 0, MUX_DDR_MODE = 1 << 1, MUX_PGP_CSPI_BB = 1 << 2, MUX_PGP_ATA_1 = 1 << 3, MUX_PGP_ATA_2 = 1 << 4, MUX_PGP_ATA_3 = 1 << 5, MUX_PGP_ATA_4 = 1 << 6, MUX_PGP_ATA_5 = 1 << 7, MUX_PGP_ATA_6 = 1 << 8, MUX_PGP_ATA_7 = 1 << 9, MUX_PGP_ATA_8 = 1 << 10, MUX_PGP_UH2 = 1 << 11, MUX_SDCTL_CSD0_SEL = 1 << 12, MUX_SDCTL_CSD1_SEL = 1 << 13, MUX_CSPI1_UART3 = 1 << 14, MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, MUX_TAMPER_DETECT_EN = 1 << 16, MUX_PGP_USB_4WIRE = 1 << 17, MUX_PGP_USB_COMMON = 1 << 18, MUX_SDHC_MEMSTICK1 = 1 << 19, MUX_SDHC_MEMSTICK2 = 1 << 20, MUX_PGP_SPLL_BYP = 1 << 21, MUX_PGP_UPLL_BYP = 1 << 22, MUX_PGP_MSHC1_CLK_SEL = 1 << 23, MUX_PGP_MSHC2_CLK_SEL = 1 << 24, MUX_CSPI3_UART5_SEL = 1 << 25, MUX_PGP_ATA_9 = 1 << 26, MUX_PGP_USB_SUSPEND = 1 << 27, MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, MUX_CLKO_DDR_MODE = 1 << 31, }; /* * setups a single pin: * - reserves the pin so that it is not claimed by another driver * - setups the iomux according to the configuration * - if the pin is configured as a GPIO, we claim it through kernel gpiolib */ int mxc_iomux_alloc_pin(unsigned int pin, const char *label); /* * setups mutliple pins * convenient way to call the above function with tables */ int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, const char *label); /* * releases a single pin: * - make it available for a future use by another driver * - frees the GPIO if the pin was configured as GPIO * - DOES NOT reconfigure the IOMUX in its reset state */ void mxc_iomux_release_pin(unsigned int pin); /* * releases multiple pins * convenvient way to call the above function with tables */ void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count); /* * This function enables/disables the general purpose function for a particular * signal. */ void mxc_iomux_set_gpr(enum iomux_gp_func, bool en); /* * This function only configures the iomux hardware. * It is called by the setup functions and should not be called directly anymore. * It is here visible for backward compatibility */ int mxc_iomux_mode(unsigned int pin_mode); #define IOMUX_PADNUM_MASK 0x1ff #define IOMUX_GPIONUM_SHIFT 9 #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) #define IOMUX_MODE_SHIFT 17 #define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) #define IOMUX_PIN(gpionum, padnum) \ (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ (padnum & IOMUX_PADNUM_MASK)) #define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) #define IOMUX_TO_GPIO(iomux_pin) \ ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) /* * This enumeration is constructed based on the Section * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated * value is constructed based on the rules described above. */ enum iomux_pins { MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), MX31_PIN_READ = IOMUX_PIN(0xff, 24), MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), MX31_PIN_SER_RS = IOMUX_PIN(89, 27), MX31_PIN_LCS1 = IOMUX_PIN(88, 28), MX31_PIN_LCS0 = IOMUX_PIN(87, 29), MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), MX31_PIN_USB_OC = IOMUX_PIN(30, 74), MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), MX31_PIN_TDO = IOMUX_PIN(0xff, 79), MX31_PIN_TDI = IOMUX_PIN(0xff, 80), MX31_PIN_TMS = IOMUX_PIN(0xff, 81), MX31_PIN_TCK = IOMUX_PIN(0xff, 82), MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), MX31_PIN_TXD2 = IOMUX_PIN(28, 103), MX31_PIN_RXD2 = IOMUX_PIN(27, 104), MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), MX31_PIN_CTS1 = IOMUX_PIN(39, 114), MX31_PIN_RTS1 = IOMUX_PIN(38, 115), MX31_PIN_TXD1 = IOMUX_PIN(37, 116), MX31_PIN_RXD1 = IOMUX_PIN(36, 117), MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),