/*********************************** * $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ *********************************** * *************************************** * Definitions of QUICC memory structures *************************************** */ #ifndef __M68360_QUICC_H #define __M68360_QUICC_H /* * include registers and * parameter ram definitions files */ #include #include /* Buffer Descriptors */ typedef struct quicc_bd { volatile unsigned short status; volatile unsigned short length; volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */ } QUICC_BD; #ifdef MOTOROLA_ORIGINAL struct user_data { /* BASE + 0x000: user data memory */ volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ volatile unsigned char udata_bd[0x200]; /*user data Ucode */ volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */ volatile unsigned char RESERVED1[0x500]; /* Reserved area */ }; #else struct user_data { /* BASE + 0x000: user data memory */ volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/ volatile unsigned char udata_bd1[0x200]; /* user, bds */ volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */ volatile unsigned char udata_bd2[0x100]; /* user, bds */ volatile unsigned char RESERVED1[0x400]; /* Reserved area */ }; #endif /* * internal ram */ typedef struct quicc { union { struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */ struct user_data u; }ch_or_u; /* multipul or user space */ /* BASE + 0xc00: PARAMETER RAM */ union { struct scc_pram { union { struct hdlc_pram h; struct uart_pram u; struct bisync_pram b; struct transparent_pram t; unsigned char RESERVED66[0x70]; } pscc; /* scc parameter area (protocol dependent) */ union { struct { unsigned char RESERVED70[0x10]; struct spi_pram spi; unsigned char RESERVED72[0x8]; struct timer_pram timer; } timer_spi; struct { struct idma_pram idma; unsigned char RESERVED67[0x4]; union { struct smc_uart_pram u; struct smc_trnsp_pram t; } psmc; } idma_smc; } pothers; } scc; struct ethernet_pram enet_scc; struct global_multi_pram m; unsigned char pr[0x100]; } pram[4]; /* reserved */ /* BASE + 0x1000: INTERNAL REGISTERS */ /* SIM */ volatile unsigned long sim_mcr; /* module configuration reg */ volatile unsigned short sim_simtr; /* module test register */ volatile unsigned char RESERVED2[0x2]; /* Reserved area */ volatile unsigned char sim_avr; /* auto vector reg */ volatile unsigned char sim_rsr; /* reset status reg */ volatile unsigned char RESERVED3[0x2]; /* Reserved area */ volatile unsigned char sim_clkocr; /* CLCO control register */ volatile unsigned char RESERVED62[0x3]; /* Reserved area */ volatile unsigned short sim_pllcr; /* PLL control register */ volatile unsigned char RESERVED63[0x2]; /* Reserved area */ volatile unsigned short sim_cdvcr; /* Clock devider control register */ volatile unsigned short sim_pepar; /* Port E pin assignment register */ volatile unsigned char RESERVED64[0xa]; /* Reserved area */ volatile unsigned char sim_sypcr; /* system protection control*/ volatile unsigned char sim_swiv; /* software interrupt vector*/ volatile unsigned char RESERVED6[0x2]; /* Reserved area */ volatile unsigned short sim_picr; /* periodic interrupt control reg */ volatile unsigned char RESERVED7[0x2]; /* Reserved area */ volatile unsigned short sim_pitr; /* periodic interrupt timing reg */ volatile unsigned char RESERVED8[0x3]; /* Reserved area */ volatile unsigned char sim_swsr; /* software service */ volatile unsigned long sim_bkar; /* breakpoint address register*/ volatile unsigned long sim_bkcr; /* breakpoint control register*/ volatile unsigned char RESERVED10[0x8]; /* Reserved area */ /* MEMC */ volatile unsigned long memc_gmr; /* Global memory register */ volatile unsigned short memc_mstat; /* MEMC status register */ volatile unsigned char RESERVED11[0xa]; /* Reserved area */ volatile unsigned long memc_br0; /* base register 0 */ volatile unsigned long memc_or0; /* option register 0 */ volatile unsigned char RESERVED12[0x8]; /* Reserved area */ volatile unsigned long memc_br1; /* base register 1 */ volatile unsigned long memc_or1; /* option register 1 */ volatile unsigned char RESERVED13[0x8]; /* Reserved area */ volatile unsigned long memc_br2; /* base register 2 */ volatile unsigned long memc_or2; /* option register 2 */ volatile unsigned char RESERVED14[0x8]; /* Reserved area */ volatile unsigned long memc_br3; /* base register 3 */ volatile unsigned long memc_or3; /* option register 3 */ volatile unsigned char RESERVED15[0x8]; /* Reserved area */ volatile unsigned long memc_br4; /* base register 3 */ volatile unsigned long memc_or4; /* option register 3 */ volatile unsigned char RESERVED16[0x8]; /* Reserved area */ volatile unsigned long memc_br5; /* base register 3 */ volatile unsigned long memc_or5; /* option register 3 */ volatile unsigned char RESERVED17[0x8]; /* Reserved area */ volatile unsigned long memc_br6; /* base register 3 */ volatile unsigned long memc_or6; /* option register 3 */ volatile unsigned char RESERVED18[0x8]; /* Reserved area */ volatile unsigned long memc_br7; /* base register 3 */ volatile unsigned long memc_or7; /* option register 3 */ volatile unsigned char RESERVED9[0x28]; /* Reserved area */ /* TEST */