/* NetWinder Floating Point Emulator (c) Rebel.COM, 1998,1999 (c) Philip Blundell, 2001 Direct questions, comments to Scott Bambrough This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __FPOPCODE_H__ #define __FPOPCODE_H__ /* ARM Floating Point Instruction Classes | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2) | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPDT data transfer instructions LDF, STF, LFM (copro 2), SFM (copro 2) CPDO dyadic arithmetic instructions ADF, MUF, SUF, RSF, DVF, RDF, POW, RPW, RMF, FML, FDV, FRD, POL CPDO monadic arithmetic instructions MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN, URD, NRM CPRT joint arithmetic/data transfer instructions FIX (arithmetic followed by load/store) FLT (load/store followed by arithmetic) CMF, CNF CMFE, CNFE (comparisons) WFS, RFS (write/read floating point status register) WFC, RFC (write/read floating point control register) cond condition codes P pre/post index bit: 0 = postindex, 1 = preindex U up/down bit: 0 = stack grows down, 1 = stack grows up W write back bit: 1 = update base register (Rn) L load/store bit: 0 = store, 1 = load Rn base register Rd destination/source register Fd floating point destination register Fn floating point source register Fm floating point source register or floating point constant uv transfer length (TABLE 1) wx register count (TABLE 2) abcd arithmetic opcode (TABLES 3 & 4) ef destination size (rounding precision) (TABLE 5) gh rounding mode (TABLE 6) j dyadic/monadic bit: 0 = dyadic, 1 = monadic i constant bit: 1 = constant (TABLE 6) */ /* TABLE 1 +-------------------------+---+---+---------+---------+ | Precision | u | v | FPSR.EP | length | +-------------------------+---+---+---------+---------+ | Single | 0 | 0 | x | 1 words | | Double | 1 | 1 | x | 2 words | | Extended | 1 | 1 | x | 3 words | | Packed decimal | 1 | 1 | 0 | 3 words | | Expanded packed decimal | 1 | 1 | 1 | 4 words | +-------------------------+---+---+---------+---------+ Note: x = don't care */ /* TABLE 2 +---+---+---------------------------------+ | w | x | Number of registers to transfer | +---+---+---------------------------------+ | 0 | 1 | 1 | | 1 | 0 | 2 | | 1 | 1 | 3 | | 0 | 0 | 4 | +---+---+---------------------------------+ */ /* TABLE 3: Dyadic Floating Point Opcodes +---+---+---+---+----------+-----------------------+-----------------------+ | a | b | c | d | Mnemonic | Description | Operation | +---+---+---+---+----------+-----------------------+-----------------------+ | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm | | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm | | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm | | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn | | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm | | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn | | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm | | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn | | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) | | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm | | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm | | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn | | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) | | 1 | 1 | 0 | 1 | | undefined instruction | trap | | 1 | 1 | 1 | 0 | | undefined instruction | trap | | 1 | 1 | 1 | 1 | | undefined instruction | trap | +---+---+---+---+----------+-----------------------+-----------------------+ Note: POW, RPW, POL are deprecated, and are available for backwards compatibility only. */ /* TABLE 4: Monadic Floating Point Opcodes +---+---+---+---+----------+-----------------------+-----------------------+ | a | b | c | d | Mnemonic | Description | Operation | +---+---+---+---+----------+-----------------------+-----------------------+ | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm | | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm | | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) | | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) | | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) | | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) | | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) | | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm | | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) | | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) | | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) | | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) | | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) | | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) | | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) | | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) | +---+---+---+---+----------+-----------------------+-----------------------+ Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are available for backwards compatibility only. */ /* TABLE 5 +-------------------------+---+---+ | Rounding Precision | e | f | +-------------------------+---+---+ | IEEE Single precision | 0 | 0 | | IEEE Double precision | 0 | 1 | | IEEE Extended precision | 1 | 0 | | undefined (trap) | 1 | 1 | +-------------------------+---+---+ */ /* TABLE 5 +---------------------------------+---+---+ | Rounding Mode | g | h | +---------------------------------+---+---+ | Round to nearest (default) | 0 | 0 | | Round toward plus infinity | 0 | 1 | | Round toward negative infinity | 1 | 0 | | Round toward zero | 1 | 1 | +---------------------------------+---+---+ */ /* === === Definitions for load and store instructions === */ /* bit masks */ #define BIT_PREINDEX 0x01000000 #define BIT_UP 0x00800000 #define BIT_WRITE_BACK 0x00200000 #define BIT_LOAD 0x00100000 /* masks for load/store */ #define MASK_CPDT 0x0c000000 /* data processing opcode */ #define MASK_OFFSET 0x000000ff #define MASK_TRANSFER_LENGTH 0x00408000 #define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH #define MASK_COPROCESSOR 0x00000f00 /* Tests for transfer length */ #define TRANSFER_SINGLE 0x00000000