/* * Copyright 2011 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #ifndef _CDEF_BF60X_H #define _CDEF_BF60X_H /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */ /* ************************************************************** */ /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ /* SEC0 Registers */ #define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL) #define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val) #define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID) #define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val) #define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL) #define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val) #define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL) #define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val) #define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8)) #define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val) #define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8)) #define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val) /* RCU0 Registers */ #define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL) #define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val) /* Watchdog Timer Registers */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) /* RTC Registers */ /* UART0 Registers */ #define bfin_read_UART0_REVID() bfin_read32(UART0_REVID) #define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val) #define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val) #define bfin_read_UART0_STAT() bfin_read32(UART0_STAT) #define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val) #define bfin_read_UART0_SCR() bfin_read32(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val) #define bfin_read_UART0_CLK() bfin_read32(UART0_CLK) #define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val) #define bfin_read_UART0_IER() bfin_read32(UART0_IER) #define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val) #define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET) #define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val) #define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR) #define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val) #define bfin_read_UART0_RBR() bfin_read32(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val) #define bfin_read_UART0_THR() bfin_read32(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val) #define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP) #define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val) #define bfin_read_UART0_TSR() bfin_read32(UART0_TSR) #define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val) #define bfin_read_UART0_RSR() bfin_read32(UART0_RSR) #define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val) #define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT) #define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val) #define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT) #define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val) /* UART1 Registers */ #define bfin_read_UART1_REVID() bfin_read32(UART1_REVID) #define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val) #define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL) #define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val) #define bfin_read_UART1_STAT() bfin_read32(UART1_STAT) #define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val) #define bfin_read_UART1_SCR() bfin_read32(UART1_SCR) #define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val) #define bfin_read_UART1_CLK() bfin_read32(UART1_CLK) #define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val) #define bfin_read_UART1_IER() bfin_read32(UART1_IER) #define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val) #define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET) #define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val) #define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR) #define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val) #define bfin_read_UART1_RBR() bfin_read32(UART1_RBR) #define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val) #define bfin_read_UART1_THR() bfin_read32(UART1_THR) #define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val) #define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP) #define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val) #define bfin_read_UART1_TSR() bfin_read32(UART1_TSR) #define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val) #define bfin_read_UART1_RSR() bfin_read32(UART1_RSR) #define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val) #define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT) #define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val) #define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT) #define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val) /* SPI0 Registers */ #define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL) #define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val) #define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL) #define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val) #define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL) #define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val) #define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK) #define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val) #define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY) #define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val) #define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL) #define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val) #define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC) #define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val) #define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR) #define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val) #define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC) #define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val) #define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR) #define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val) #define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK) #define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val) #define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR) #define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val) #define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET) #define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val) #define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT) #define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val) #define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT) #define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val) #define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR) #define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val) #define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO) #define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val) #define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO) #define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val) /* SPI1 Registers */ #define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL) #define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val) #define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL) #define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val) #define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL) #define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val) #define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK) #define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val) #define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY) #define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val) #define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL) #define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val) #define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC) #define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val) #define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR) #define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val) #define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC) #define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val) #define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR) #define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val) #define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK) #define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val) #define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR) #define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val) #define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET) #define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val) #define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT) #define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val) #define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT) #define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val) #define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR) #define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val) #define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO) #define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val) #define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO) #define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val) /* Timer 0-7 registers */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) /* Two Wire Interface Registers (TWI0) */ /* SPORT1 Registers */ /* SMC Registers */ #define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL) #define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val) #define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT) #define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL) #define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val) #define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM) #define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val) #define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM) #define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val) #define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL) #define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val) #define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM) #define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val) #define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM) #define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val) #define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL) #define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val) #define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM) #define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val) #define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM) #define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val) #define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL) #define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val) #define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM) #define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val) #define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM) #define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val) /* DDR2 Memory Control Registers */ #define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG) #define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val) #define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0) #define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val) #define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1) #define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val) #define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2) #define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val) #define bfin_read_DMC0_MR() bfin_read32(DMC0_MR) #define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val) #define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1) #define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) #define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) #define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) #define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) #define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) #define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL) #define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val) /* DDR BankRead and Write Count Registers */ /* DMA Channel 0 Registers */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) #define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val) #define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val) #define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val) #define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val) #define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val) #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) #define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR) #define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val) #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) #define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val) #define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val) #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val) #define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT) #define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val) #define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT) #define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val) #define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT) #define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val) #define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT) #define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val) /* DMA Channel 1 Registers */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) #define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val) #define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val) #define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val) #define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val) #define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val) #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) #define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR) #define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val) #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) #define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val) #define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val) #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val) #define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT) #define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val) #define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT) #define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val) #define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT) #define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val) #define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT) #define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val) /* DMA Channel 2 Registers */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) #define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val) #define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val) #define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val) #define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val) #define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val) #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) #define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR) #define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val) #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) #define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val) #define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val) #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val) #define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT) #define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val) #define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT) #define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val) #define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT) #define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val) #define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT) #define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val) /* DMA Channel 3 Registers */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) #define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val) #define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val) #define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val) #define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val) #define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val) #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) #define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR) #define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val) #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) #define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val) #define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val) #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val) #define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT) #define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val) #define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT) #define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val) #define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT) #define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val) #define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT) #define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val) /* DMA Channel 4 Registers */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) #define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val) #define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val) #define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val) #define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val) #define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val) #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) #define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR) #define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val) #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) #define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val) #define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val) #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val) #define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT) #define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val) #define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT) #define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val) #define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT) #define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val) #define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT) #define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val) /* DMA Channel 5 Registers */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) #define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val) #define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val) #define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val) #define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val) #define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val) #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) #define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR) #define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val) #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) #define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val) #define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val) #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val) #define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT) #define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val) #define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT) #define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val) #define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT) #define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val) #define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT) #define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val) /* DMA Channel 6 Registers */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) #define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val) #define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val) #define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val) #define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val) #define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val) #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) #define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR) #define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val) #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) #define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val) #define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val) #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val) #define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT) #define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val) #define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT) #define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val) #define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT) #define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val) #define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT) #define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val) /* DMA Channel 7 Registers */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) #define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val) #define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val) #define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val) #define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val) #define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val) #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) #define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR) #define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val) #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) #define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val) #define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val) #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val) #define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT) #define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val) #define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT) #define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val) #define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT) #define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val) #define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT) #define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val) /* DMA Channel 8 Registers */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) #define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val) #define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val) #define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val) #define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val) #define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val) #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) #define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR) #define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val) #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) #define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val) #define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT) #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val) #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT) #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val) #define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT) #define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val) #define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT) #define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val) #define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT) #define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val) #define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT) #define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val) /* DMA Channel 9 Registers */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) #define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val) #define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val) #define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY) #define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val) #define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val) #define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY) #define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val) #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) #define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR) #define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val) #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) #define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS)