/* * linux/arch/arm/mach-versatile/core.c * * Copyright (C) 1999 - 2003 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "core.h" /* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx * is the (PA >> 12). * * Setup a VA for the Versatile Vectored Interrupt Controller. */ #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) /* These PIC IRQs are valid in each configuration */ #define PIC_VALID_ALL BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \ BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \ BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \ BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \ BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \ BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \ BIT(SIC_INT_PCI3) #if 1 #define IRQ_MMCI0A IRQ_VICSOURCE22 #define IRQ_AACI IRQ_VICSOURCE24 #define IRQ_ETH IRQ_VICSOURCE25 #define PIC_MASK 0xFFD00000 #define PIC_VALID PIC_VALID_ALL #else #define IRQ_MMCI0A IRQ_SIC_MMCI0A #define IRQ_AACI IRQ_SIC_AACI #define IRQ_ETH IRQ_SIC_ETH #define PIC_MASK 0 #define PIC_VALID PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \ BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \ BIT(SIC_INT_ETH) #endif /* Lookup table for finding a DT node that represents the vic instance */ static const struct of_device_id vic_of_match[] __initconst = { { .compatible = "arm,versatile-vic", }, {} }; static const struct of_device_id sic_of_match[] __initconst = { { .compatible = "arm,versatile-sic", }, {} }; void __init versatile_init_irq(void) { struct device_node *np; np = of_find_matching_node_by_address(NULL, vic_of_match, VERSATILE_VIC_BASE); __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np); writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); np = of_find_matching_node_by_address(NULL, sic_of_match, VERSATILE_SIC_BASE); fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START, IRQ_VICSOURCE31, PIC_VALID, np); /* * Interrupts on secondary controller from 0 to 8 are routed to * source 31 on PIC. * Interrupts from 21 to 31 are routed directly to the VIC on * the corresponding number on primary controller. This is controlled * by setting PIC_ENABLEx. */ writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE); } static struct map_desc versatile_io_desc[] __initdata = { { .virtual = IO_ADDRESS(VERSATILE_SYS_BASE), .pfn = __phys_to_pfn(VERSATILE_SYS_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = IO_ADDRESS(VERSATILE_SIC_BASE), .pfn = __phys_to_pfn(VERSATILE_SIC_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = IO_ADDRESS(VERSATILE_VIC_BASE), .pfn = __phys_to_pfn(VERSATILE_VIC_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE), .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE), .length = SZ_4K * 9, .type = MT_DEVICE }, #ifdef CONFIG_MACH_VERSATILE_AB { .virtual = IO_ADDRESS(VERSATILE_IB2_BASE), .pfn = __phys_to_pfn(VERSATILE_IB2_BASE), .length = SZ_64M, .type = MT_DEVICE }, #endif #ifdef CONFIG_DEBUG_LL { .virtual = IO_ADDRESS(VERSATILE_UART0_BASE), .pfn = __phys_to_pfn(VERSATILE_UART0_BASE), .length = SZ_4K, .type = MT_DEVICE }, #endif #ifdef CONFIG_PCI { .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE), .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE, .pfn = __phys_to_pfn(VERSATILE_PCI_BASE), .length = VERSATILE_PCI_BASE_SIZE, .type = MT_DEVICE }, { .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE, .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE), .length = VERSATILE_PCI_CFG_BASE_SIZE, .type = MT_DEVICE }, #endif }; void __init versatile_map_io(void) { iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc)); } #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) static void versatile_flash_set_vpp(struct platform_device *pdev, int on) { u32 val; val = __raw_readl(VERSATILE_FLASHCTRL); if (on) val |= VERSATILE_FLASHPROG_FLVPPEN; else val &= ~VERSATILE_FLASHPROG_FLVPPEN; __raw_writel(val, VERSATILE_FLASHCTRL); } static struct physmap_flash_data versatile_flash_data = { .width = 4, .set_vpp = versatile_flash_set_vpp, }; static struct resource versatile_flash_resource = { .start = VERSATILE_FLASH_BASE, .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1, .flags = IORESOURCE_MEM, }; static struct platform_device versatile_flash_device = { .name = "physmap-flash", .id = 0, .dev = { .platform_data = &versatile_flash_data, }, .num_resources = 1, .resource = &versatile_flash_resource, }; static struct resource smc91x_resources[] = { [0] = { .start = VERSATILE_ETH_BASE, .end = VERSATILE_ETH_BASE + SZ_64K - 1, .flags = IORESOURCE_MEM, }, [1] = { .start = IRQ_ETH, .end = IRQ_ETH, .flags = IORESOURCE_IRQ, }, }; static struct platform_device smc91x_device = { .name = "smc91x", .id = 0, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, }; static struct resource versatile_i2c_resource = { .start = VERSATILE_I2C_BASE, .end = VERSATILE_I2C_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }; static struct platform_device versatile_i2c_device = { .name = "versatile-i2c", .id = 0, .num_resources = 1, .resource = &versatile_i2c_resource, }; static struct i2c_board_info versatile_i2c_board_info[] = { { I2C_BOARD_INFO("ds1338", 0xd0 >> 1), }, }; static int __init versatile_i2c_init(void) { return i2c_register_board_info(0, versatile_i2c_board_info, ARRAY_SIZE(versatile_i2c_board_info)); } arch_initcall(versatile_i2c_init); #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) unsigned int mmc_status(struct device *dev) { struct amba_device *adev = container_of(dev, struct amba_device, dev); u32 mask; if (adev->res.start == VERSATILE_MMCI0_BASE) mask = 1; else mask = 2; return readl(VERSATILE_SYSMCI) & mask; } static struct mmci_platform_data mmc0_plat_data = { .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .status = mmc_status, .gpio_wp = -1, .gpio_cd = -1, }; static struct resource char_lcd_resources[] = { { .start = VERSATILE_CHAR_LCD_BASE, .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1), .flags = IORESOURCE_MEM, }, }; static struct platform_device char_lcd_device = { .name = "arm-charlcd", .id = -1, .num_resources = ARRAY_SIZE(char_lcd_resources), .resource = char_lcd_resources, }; /* * Clock handling */ static const struct icst_params versatile_oscvco_params = { .ref = 24000000, .vco_max = ICST307_VCO_MAX, .vco_min = ICST307_VCO_MIN, .vd_min = 4 + 8, .vd_max = 511 + 8, .rd_min = 1 + 2, .rd_max = 127 + 2, .s2div = icst307_s2div, .idx2s = icst307_idx2s, }; static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco) { void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET; u32 val; val = readl(clk->vcoreg) & ~0x7ffff; val |= vco.v | (vco.r << 9) | (vco.s << 16); writel(0xa05f, sys_lock); writel(val, clk->vcoreg); writel(0, sys_lock); } static const struct clk_ops osc4_clk_ops = { .round = icst_clk_round, .set = icst_clk_set, .setvco = versatile_oscvco_set, }; static struct clk osc4_clk = { .ops = &osc4_clk_ops, .params = &versatile_oscvco_params, }; /* * These are fixed clocks. */ static struct clk ref24_clk = { .rate = 24000000, }; static struct clk sp804_clk = { .rate = 1000000, }; static struct clk dummy_apb_pclk; static struct clk_lookup lookups[] = { { /* AMBA bus clock */ .con_id = "apb_pclk", .clk = &dummy_apb_pclk, }, { /* UART0 */ .dev_id = "dev:f1", .clk = &ref24_clk, }, { /* UART1 */ .dev_id = "dev:f2", .clk = &ref24_clk, }, { /* UART2 */ .dev_id = "dev:f3", .clk = &ref24_clk, }, { /* UART3 */ .dev_id = "fpga:09", .clk = &ref24_clk, }, { /* KMI0 */ .dev_id = "fpga:06", .clk = &ref24_clk, }, { /* KMI1 */ .dev_id = "fpga:07", .clk = &ref24_clk, }, { /* MMC0 */ .dev_id = "fpga:05", .clk = &ref24_clk, }, { /* MMC1 */ .dev_id = "fpga:0b", .clk = &ref24_clk, }, { /* SSP */ .dev_id = "dev:f4", .clk = &ref24_clk, }, { /* CLCD */ .dev_id = "dev:20", .clk = &osc4_clk, }, { /* SP804 timers */ .dev_id = "sp804", .clk = &sp804_clk, }, }; /* * CLCD support. */ #define SYS_CLCD_MODE_MASK (3 << 0) #define SYS_CLCD_MODE_888 (0 << 0) #define SYS_CLCD_MODE_5551 (1 << 0) #define SYS_CLCD_MODE_565_RLSB (2 << 0) #define SYS_CLCD_MODE_565_BLSB (3 << 0) #define SYS_CLCD_NLCDIOON (1 << 2) #define SYS_CLCD_VDDPOSSWITCH (1 << 3) #define SYS_CLCD_PWR3V5SWITCH (1 << 4) #define SYS_CLCD_ID_MASK (0x1f << 8) #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) #define SYS_CLCD_ID_VGA (0x1f << 8) static bool is_sanyo_2_5_lcd; /* * Disable all display connectors on the interface module. */ static void versatile_clcd_disable(struct clcd_fb *fb) { void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; u32 val; val = readl(sys_clcd); val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; writel(val, sys_clcd); #ifdef CONFIG_MACH_VERSATILE_AB /* * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off */ if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) { void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); unsigned long ctrl; ctrl = readl(versatile_ib2_ctrl); ctrl &= ~0x01; writel(ctrl, versatile_ib2_ctrl); } #endif } /* * Enable the relevant connector on the interface module. */ static void versatile_clcd_enable(struct clcd_fb *fb) { struct fb_var_screeninfo *var = &fb->fb.var; void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; u32 val; val = readl(sys_clcd); val &= ~SYS_CLCD_MODE_MASK; switch (var->green.length) { case 5: val |= SYS_CLCD_MODE_5551; break; case 6: if (var->red.offset == 0) val |= SYS_CLCD_MODE_565_RLSB; else val |= SYS_CLCD_MODE_565_BLSB; break; case 8: val |= SYS_CLCD_MODE_888; break; } /* * Set the MUX */ writel(val, sys_clcd); /* * And now enable the PSUs */ val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; writel(val, sys_clcd); #ifdef CONFIG_MACH_VERSATILE_AB /* * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on */ if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) { void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); unsigned long ctrl; ctrl = readl(versatile_ib2_ctrl); ctrl |= 0x01; writel(ctrl, versatile_ib2_ctrl);