/* * sh7372 processor support - PFC hardware block * * Copyright (C) 2010 Kuninori Morimoto * * Based on * sh7367 processor support - PFC hardware block * Copyright (C) 2010 Magnus Damm * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #define CPU_ALL_PORT(fn, pfx, sfx) \ PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \ PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \ PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \ PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) enum { PINMUX_RESERVED = 0, /* PORT0_DATA -> PORT190_DATA */ PINMUX_DATA_BEGIN, PORT_ALL(DATA), PINMUX_DATA_END, /* PORT0_IN -> PORT190_IN */ PINMUX_INPUT_BEGIN, PORT_ALL(IN), PINMUX_INPUT_END, /* PORT0_IN_PU -> PORT190_IN_PU */ PINMUX_INPUT_PULLUP_BEGIN, PORT_ALL(IN_PU), PINMUX_INPUT_PULLUP_END, /* PORT0_IN_PD -> PORT190_IN_PD */ PINMUX_INPUT_PULLDOWN_BEGIN, PORT_ALL(IN_PD), PINMUX_INPUT_PULLDOWN_END, /* PORT0_OUT -> PORT190_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), PINMUX_OUTPUT_END, PINMUX_FUNCTION_BEGIN, PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT190_FN_IN */ PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT190_FN_OUT */ PORT_ALL(FN0), /* PORT0_FN0 -> PORT190_FN0 */ PORT_ALL(FN1), /* PORT0_FN1 -> PORT190_FN1 */ PORT_ALL(FN2), /* PORT0_FN2 -> PORT190_FN2 */ PORT_ALL(FN3), /* PORT0_FN3 -> PORT190_FN3 */ PORT_ALL(FN4), /* PORT0_FN4 -> PORT190_FN4 */ PORT_ALL(FN5), /* PORT0_FN5 -> PORT190_FN5 */ PORT_ALL(FN6), /* PORT0_FN6 -> PORT190_FN6 */ PORT_ALL(FN7), /* PORT0_FN7 -> PORT190_FN7 */ MSEL1CR_31_0, MSEL1CR_31_1, MSEL1CR_30_0, MSEL1CR_30_1, MSEL1CR_29_0, MSEL1CR_29_1, MSEL1CR_28_0, MSEL1CR_28_1, MSEL1CR_27_0, MSEL1CR_27_1, MSEL1CR_26_0, MSEL1CR_26_1, MSEL1CR_16_0, MSEL1CR_16_1, MSEL1CR_15_0, MSEL1CR_15_1, MSEL1CR_14_0, MSEL1CR_14_1, MSEL1CR_13_0, MSEL1CR_13_1, MSEL1CR_12_0, MSEL1CR_12_1, MSEL1CR_9_0, MSEL1CR_9_1, MSEL1CR_8_0, MSEL1CR_8_1, MSEL1CR_7_0, MSEL1CR_7_1, MSEL1CR_6_0, MSEL1CR_6_1, MSEL1CR_4_0, MSEL1CR_4_1, MSEL1CR_3_0, MSEL1CR_3_1, MSEL1CR_2_0, MSEL1CR_2_1, MSEL1CR_0_0, MSEL1CR_0_1, MSEL3CR_27_0, MSEL3CR_27_1, MSEL3CR_26_0, MSEL3CR_26_1, MSEL3CR_21_0, MSEL3CR_21_1, MSEL3CR_20_0, MSEL3CR_20_1, MSEL3CR_15_0, MSEL3CR_15_1, MSEL3CR_9_0, MSEL3CR_9_1, MSEL3CR_6_0, MSEL3CR_6_1, MSEL4CR_19_0, MSEL4CR_19_1, MSEL4CR_18_0, MSEL4CR_18_1, MSEL4CR_17_0, MSEL4CR_17_1, MSEL4CR_16_0, MSEL4CR_16_1, MSEL4CR_15_0, MSEL4CR_15_1, MSEL4CR_14_0, MSEL4CR_14_1, MSEL4CR_10_0, MSEL4CR_10_1, MSEL4CR_6_0, MSEL4CR_6_1, MSEL4CR_4_0, MSEL4CR_4_1, MSEL4CR_1_0, MSEL4CR_1_1, PINMUX_FUNCTION_END, PINMUX_MARK_BEGIN, /* IRQ */ IRQ0_6_MARK, IRQ0_162_MARK, IRQ1_MARK, IRQ2_4_MARK, IRQ2_5_MARK, IRQ3_8_MARK, IRQ3_16_MARK, IRQ4_17_MARK, IRQ4_163_MARK, IRQ5_MARK, IRQ6_39_MARK, IRQ6_164_MARK, IRQ7_40_MARK, IRQ7_167_MARK, IRQ8_41_MARK, IRQ8_168_MARK, IRQ9_42_MARK, IRQ9_169_MARK, IRQ10_MARK, IRQ11_MARK, IRQ12_80_MARK, IRQ12_137_MARK, IRQ13_81_MARK, IRQ13_145_MARK, IRQ14_82_MARK, IRQ14_146_MARK, IRQ15_83_MARK, IRQ15_147_MARK, IRQ16_84_MARK, IRQ16_170_MARK, IRQ17_MARK, IRQ18_MARK, IRQ19_MARK, IRQ20_MARK, IRQ21_MARK, IRQ22_MARK, IRQ23_MARK, IRQ24_MARK, IRQ25_MARK, IRQ26_121_MARK, IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK, IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK, IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK, /* MSIOF0 */ MSIOF0_TSYNC_MARK, MSIOF0_TSCK_MARK, MSIOF0_RXD_MARK, MSIOF0_RSCK_MARK, MSIOF0_RSYNC_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK, MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_TXD_MARK, /* MSIOF1 */ MSIOF1_TSCK_39_MARK, MSIOF1_TSYNC_40_MARK, MSIOF1_TSCK_88_MARK, MSIOF1_TSYNC_89_MARK, MSIOF1_TXD_41_MARK, MSIOF1_RXD_42_MARK, MSIOF1_TXD_90_MARK, MSIOF1_RXD_91_MARK, MSIOF1_SS1_43_MARK, MSIOF1_SS2_44_MARK, MSIOF1_SS1_92_MARK, MSIOF1_SS2_93_MARK, MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK, MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, /* MSIOF2 */ MSIOF2_RSCK_MARK, MSIOF2_RSYNC_MARK, MSIOF2_MCK0_MARK, MSIOF2_MCK1_MARK, MSIOF2_SS1_MARK, MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK, MSIOF2_TXD_MARK, /* BBIF1 */ BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK, BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK, /* BBIF2 */ BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK, BBIF2_TXD1_MARK, BBIF2_RXD_MARK, /* FSI */ FSIACK_MARK, FSIBCK_MARK, FSIAILR_MARK, FSIAIBT_MARK, FSIAISLD_MARK, FSIAOMC_MARK, FSIAOLR_MARK, FSIAOBT_MARK, FSIAOSLD_MARK, FSIASPDIF_11_MARK, FSIASPDIF_15_MARK, /* FMSI */ FMSOCK_MARK, FMSOOLR_MARK, FMSIOLR_MARK, FMSOOBT_MARK, FMSIOBT_MARK, FMSOSLD_MARK, FMSOILR_MARK, FMSIILR_MARK, FMSOIBT_MARK, FMSIIBT_MARK, FMSISLD_MARK, FMSICK_MARK, /* SCIFA0 */ SCIFA0_TXD_MARK, SCIFA0_RXD_MARK, SCIFA0_SCK_MARK, SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, /* SCIFA1 */ SCIFA1_TXD_MARK, SCIFA1_RXD_MARK, SCIFA1_SCK_MARK, SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, /* SCIFA2 */ SCIFA2_CTS1_MARK, SCIFA2_RTS1_MARK, SCIFA2_TXD1_MARK, SCIFA2_RXD1_MARK, SCIFA2_SCK1_MARK, /* SCIFA3 */ SCIFA3_CTS_43_MARK, SCIFA3_CTS_140_MARK, SCIFA3_RTS_44_MARK, SCIFA3_RTS_141_MARK, SCIFA3_SCK_MARK, SCIFA3_TXD_MARK, SCIFA3_RXD_MARK, /* SCIFA4 */ SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, /* SCIFA5 */ SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, /* SCIFB */ SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK, SCIFB_TXD_MARK, SCIFB_RXD_MARK, /* CEU */ VIO_HD_MARK, VIO_CKO1_MARK, VIO_CKO2_MARK, VIO_VD_MARK, VIO_CLK_MARK, VIO_FIELD_MARK, VIO_CKO_MARK, VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, /* USB0 */ IDIN_0_MARK, EXTLP_0_MARK, OVCN2_0_MARK, PWEN_0_MARK, OVCN_0_MARK, VBUS0_0_MARK, /* USB1 */ IDIN_1_18_MARK, IDIN_1_113_MARK, PWEN_1_115_MARK, PWEN_1_138_MARK, OVCN_1_114_MARK, OVCN_1_162_MARK, EXTLP_1_MARK, OVCN2_1_MARK, VBUS0_1_MARK, /* GPIO */ GPI0_MARK, GPI1_MARK, GPO0_MARK, GPO1_MARK, /* BSC */ BS_MARK, WE1_MARK, CKO_MARK, WAIT_MARK, RDWR_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK, A12_MARK, A13_MARK, A14_MARK, A15_MARK, A16_MARK, A17_MARK, A18_MARK, A19_MARK, A20_MARK, A21_MARK, A22_MARK, A23_MARK, A24_MARK, A25_MARK, A26_MARK, CS0_MARK, CS2_MARK, CS4_MARK, CS5A_MARK, CS5B_MARK, CS6A_MARK, /* BSC/FLCTL */ RD_FSC_MARK, WE0_FWE_MARK, A4_FOE_MARK, A5_FCDE_MARK, D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, /* MMCIF(1) */ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, MMCCMD0_MARK, MMCCLK0_MARK, /* MMCIF(2) */ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, MMCCLK1_MARK, MMCCMD1_MARK, /* SPU2 */ VINT_I_MARK, /* FLCTL */ FCE1_MARK, FCE0_MARK, FRB_MARK, /* HSI */ GP_RX_FLAG_MARK, GP_RX_DATA_MARK, GP_TX_READY_MARK, GP_RX_WAKE_MARK, MP_TX_FLAG_MARK, MP_TX_DATA_MARK, MP_RX_READY_MARK, MP_TX_WAKE_MARK, /* MFI */ MFIv6_MARK, MFIv4_MARK, MEMC_CS0_MARK, MEMC_BUSCLK_MEMC_A0_MARK, MEMC_CS1_MEMC_A1_MARK, MEMC_ADV_MEMC_DREQ0_MARK, MEMC_WAIT_MEMC_DREQ1_MARK, MEMC_NOE_MARK, MEMC_NWE_MARK, MEMC_INT_MARK, MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK, MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK, MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK, MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK, /* SIM */ SIM_RST_MARK, SIM_CLK_MARK, SIM_D_MARK, /* TPU */ TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO2_93_MARK, TPU0TO2_99_MARK, TPU0TO3_MARK, /* I2C2 */ I2C_SCL2_MARK, I2C_SDA2_MARK, /* I2C3(1) */ I2C_SCL3_MARK, I2C_SDA3_MARK, /* I2C3(2) */ I2C_SCL3S_MARK, I2C_SDA3S_MARK, /* I2C4(2) */ I2C_SCL4_MARK, I2C_SDA4_MARK, /* I2C4(2) */ I2C_SCL4S_MARK, I2C_SDA4S_MARK, /* KEYSC */ KEYOUT0_MARK, KEYIN0_121_MARK, KEYIN0_136_MARK, KEYOUT1_MARK, KEYIN1_122_MARK, KEYIN1_135_MARK, KEYOUT2_MARK, KEYIN2_123_MARK, KEYIN2_134_MARK, KEYOUT3_MARK, KEYIN3_124_MARK, KEYIN3_133_MARK, KEYOUT4_MARK, KEYIN4_MARK, KEYOUT5_MARK, KEYIN5_MARK, KEYOUT6_MARK, KEYIN6_MARK, KEYOUT7_MARK, KEYIN7_MARK, /* LCDC */ LCDC0_SELECT_MARK, LCDC1_SELECT_MARK, LCDHSYN_MARK, LCDCS_MARK, LCDVSYN_MARK, LCDDCK_MARK, LCDWR_MARK, LCDRD_MARK, LCDDISP_MARK, LCDRS_MARK, LCDLCLK_MARK, LCDDON_MARK, LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, /* IRDA */ IRDA_OUT_MARK, IRDA_IN_MARK, IRDA_FIRSEL_MARK, IROUT_139_MARK, IROUT_140_MARK, /* TSIF1 */ TS0_1SELECT_MARK, TS0_2SELECT_MARK, TS1_1SELECT_MARK, TS1_2SELECT_MARK, TS_SPSYNC1_MARK, TS_SDAT1_MARK, TS_SDEN1_MARK, TS_SCK1_MARK, /* TSIF2 */ TS_SPSYNC2_MARK, TS_SDAT2_MARK, TS_SDEN2_MARK, TS_SCK2_MARK, /* HDMI */ HDMI_HPD_MARK, HDMI_CEC_MARK, /* SDHI0 */ SDHICLK0_MARK, SDHICD0_MARK, SDHICMD0_MARK, SDHIWP0_MARK, SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, /* SDHI1 */ SDHICLK1_MARK, SDHICMD1_MARK, SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, /* SDHI2 */ SDHICLK2_MARK, SDHICMD2_MARK, SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, /* SDENC */ SDENC_CPG_MARK, SDENC_DV_CLKI_MARK, PINMUX_MARK_END, }; static pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), PORT_DATA_O(2), PORT_DATA_I_PD(3), PORT_DATA_I_PD(4), PORT_DATA_I_PD(5), PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7), PORT_DATA_IO_PD(8), PORT_DATA_O(9), PORT_DATA_O(10), PORT_DATA_O(11), PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13), PORT_DATA_IO_PD(14), PORT_DATA_O(15), PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), PORT_DATA_I_PD(18), PORT_DATA_IO(19), PORT_DATA_IO(20), PORT_DATA_IO(21), PORT_DATA_IO(22), PORT_DATA_IO(23), PORT_DATA_IO(24), PORT_DATA_IO(25), PORT_DATA_IO(26), PORT_DATA_IO(27), PORT_DATA_IO(28), PORT_DATA_IO(29), PORT_DATA_IO(30), PORT_DATA_IO(31), PORT_DATA_IO(32), PORT_DATA_IO(33), PORT_DATA_IO(34), PORT_DATA_IO(35), PORT_DATA_IO(36), PORT_DATA_IO(37), PORT_DATA_IO(38), PORT_DATA_IO(39), PORT_DATA_IO(40), PORT_DATA_IO(41), PORT_DATA_IO(42), PORT_DATA_IO(43), PORT_DATA_IO(44), PORT_DATA_IO(45), PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47), PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49), PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51), PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53), PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55), PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57), PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59), PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61), PORT_DATA_IO(62), PORT_DATA_O(63), PORT_DATA_O(64), PORT_DATA_IO_PU(65), PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/ PORT_DATA_O(68), PORT_DATA_IO(69), PORT_DATA_IO(70), PORT_DATA_IO(71), PORT_DATA_O(72), PORT_DATA_I_PU(73), PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87), PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89), PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91), PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/ PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101), PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103), PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107), PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109), PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111), PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113), PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117), PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121), PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125), PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127), PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129), PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131), PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133), PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137), PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143), PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145), PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147), PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149), PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153), PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155), PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159), PORT_DATA_O(160), PORT_DATA_IO_PD(161), PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165), PORT_DATA_I_PD(166), PORT_DATA_I_PD(167), PORT_DATA_I_PD(168), PORT_DATA_I_PD(169), PORT_DATA_I_PD(170), PORT_DATA_O(171), PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173), PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175), PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177), PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179), PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181), PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183), PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185), PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187), PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189), PORT_DATA_IO_PU_PD(190), /* IRQ */ PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), PINMUX_DATA(IRQ0_162_MARK, PORT162_FN0, MSEL1CR_0_1), PINMUX_DATA(IRQ1_MARK, PORT12_FN0), PINMUX_DATA(IRQ2_4_MARK, PORT4_FN0, MSEL1CR_2_0), PINMUX_DATA(IRQ2_5_MARK, PORT5_FN0, MSEL1CR_2_1), PINMUX_DATA(IRQ3_8_MARK, PORT8_FN0, MSEL1CR_3_0), PINMUX_DATA(IRQ3_16_MARK, PORT16_FN0, MSEL1CR_3_1), PINMUX_DATA(IRQ4_17_MARK, PORT17_FN0, MSEL1CR_4_0), PINMUX_DATA(IRQ4_163_MARK, PORT163_FN0, MSEL1CR_4_1), PINMUX_DATA(IRQ5_MARK, PORT18_FN0), PINMUX_DATA(IRQ6_39_MARK, PORT39_FN0, MSEL1CR_6_0), PINMUX_DATA(IRQ6_164_MARK, PORT164_FN0, MSEL1CR_6_1), PINMUX_DATA(IRQ7_40_MARK, PORT40_FN0, MSEL1CR_7_1), PINMUX_DATA(IRQ7_167_MARK, PORT167_FN0, MSEL1CR_7_0), PINMUX_DATA(IRQ8_41_MARK, PORT41_FN0, MSEL1CR_8_1), PINMUX_DATA(IRQ8_168_MARK, PORT168_FN0, MSEL1CR_8_0), PINMUX_DATA(IRQ9_42_MARK, PORT42_FN0, MSEL1CR_9_0), PINMUX_DATA(IRQ9_169_MARK, PORT169_FN0, MSEL1CR_9_1), PINMUX_DATA(IRQ10_MARK, PORT65_FN0, MSEL1CR_9_1), PINMUX_DATA(IRQ11_MARK, PORT67_FN0), PINMUX_DATA(IRQ12_80_MARK, PORT80_FN0, MSEL1CR_12_0), PINMUX_DATA(IRQ12_137_MARK, PORT137_FN0, MSEL1CR_12_1), PINMUX_DATA(IRQ13_81_MARK, PORT81_FN0, MSEL1CR_13_0), PINMUX_DATA(IRQ13_145_MARK, PORT145_FN0, MSEL1CR_13_1), PINMUX_DATA(IRQ14_82_MARK, PORT82_FN0, MSEL1CR_14_0), PINMUX_DATA(IRQ14_146_MARK, PORT146_FN0, MSEL1CR_14_1), PINMUX_DATA(IRQ15_83_MARK, PORT83_FN0, MSEL1CR_15_0), PINMUX_DATA(IRQ15_147_MARK, PORT147_FN0, MSEL1CR_15_1), PINMUX_DATA(IRQ16_84_MARK, PORT84_FN0, MSEL1CR_16_0), PINMUX_DATA(IRQ16_170_MARK, PORT170_FN0, MSEL1CR_16_1), PINMUX_DATA(IRQ17_MARK, PORT85_FN0), PINMUX_DATA(IRQ18_MARK, PORT86_FN0), PINMUX_DATA(IRQ19_MARK, PORT87_FN0), PINMUX_DATA(IRQ20_MARK, PORT92_FN0), PINMUX_DATA(IRQ21_MARK, PORT93_FN0), PINMUX_DATA(IRQ22_MARK, PORT94_FN0), PINMUX_DATA(IRQ23_MARK, PORT95_FN0), PINMUX_DATA(IRQ24_MARK, PORT112_FN0), PINMUX_DATA(IRQ25_MARK, PORT119_FN0), PINMUX_DATA(IRQ26_121_MARK, PORT121_FN0, MSEL1CR_26_1), PINMUX_DATA(IRQ26_172_MARK, PORT172_FN0, MSEL1CR_26_0), PINMUX_DATA(IRQ27_122_MARK, PORT122_FN0, MSEL1CR_27_1), PINMUX_DATA(IRQ27_180_MARK, PORT180_FN0, MSEL1CR_27_0), PINMUX_DATA(IRQ28_123_MARK, PORT123_FN0, MSEL1CR_28_1), PINMUX_DATA(IRQ28_181_MARK, PORT181_FN0, MSEL1CR_28_0), PINMUX_DATA(IRQ29_129_MARK, PORT129_FN0, MSEL1CR_29_1), PINMUX_DATA(IRQ29_182_MARK, PORT182_FN0, MSEL1CR_29_0), PINMUX_DATA(IRQ30_130_MARK, PORT130_FN0, MSEL1CR_30_1), PINMUX_DATA(IRQ30_183_MARK, PORT183_FN0, MSEL1CR_30_0), PINMUX_DATA(IRQ31_138_MARK, PORT138_FN0, MSEL1CR_31_1), PINMUX_DATA(IRQ31_184_MARK, PORT184_FN0, MSEL1CR_31_0), /* Function 1 */ PINMUX_DATA(BBIF2_TSCK1_MARK, PORT0_FN1), PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT1_FN1), PINMUX_DATA(BBIF2_TXD1_MARK, PORT2_FN1), PINMUX_DATA(BBIF2_RXD_MARK, PORT3_FN1), PINMUX_DATA(FSIACK_MARK, PORT4_FN1), PINMUX_DATA(FSIAILR_MARK, PORT5_FN1), PINMUX_DATA(FSIAIBT_MARK, PORT6_FN1), PINMUX_DATA(FSIAISLD_MARK, PORT7_FN1), PINMUX_DATA(FSIAOMC_MARK, PORT8_FN1), PINMUX_DATA(FSIAOLR_MARK, PORT9_FN1), PINMUX_DATA(FSIAOBT_MARK, PORT10_FN1), PINMUX_DATA(FSIAOSLD_MARK, PORT11_FN1), PINMUX_DATA(FMSOCK_MARK, PORT12_FN1), PINMUX_DATA(FMSOOLR_MARK, PORT13_FN1), PINMUX_DATA(FMSOOBT_MARK, PORT14_FN1), PINMUX_DATA(FMSOSLD_MARK, PORT15_FN1), PINMUX_DATA(FMSOILR_MARK, PORT16_FN1), PINMUX_DATA(FMSOIBT_MARK, PORT17_FN1), PINMUX_DATA(FMSISLD_MARK, PORT18_FN1), PINMUX_DATA(A0_MARK, PORT19_FN1), PINMUX_DATA(A1_MARK, PORT20_FN1), PINMUX_DATA(A2_MARK, PORT21_FN1), PINMUX_DATA(A3_MARK, PORT22_FN1), PINMUX_DATA(A4_FOE_MARK, PORT23_FN1), PINMUX_DATA(A5_FCDE_MARK, PORT24_FN1), PINMUX_DATA(A6_MARK, PORT25_FN1), PINMUX_DATA(A7_MARK, PORT26_FN1), PINMUX_DATA(A8_MARK, PORT27_FN1), PINMUX_DATA(A9_MARK, PORT28_FN1), PINMUX_DATA(A10_MARK, PORT29_FN1), PINMUX_DATA(A11_MARK, PORT30_FN1), PINMUX_DATA(A12_MARK, PORT31_FN1), PINMUX_DATA(A13_MARK, PORT32_FN1), PINMUX_DATA(A14_MARK, PORT33_FN1), PINMUX_DATA(A15_MARK, PORT34_FN1), PINMUX_DATA(A16_MARK, PORT35_FN1), PINMUX_DATA(A17_MARK, PORT36_FN1), PINMUX_DATA(A18_MARK, PORT37_FN1), PINMUX_DATA(A19_MARK, PORT38_FN1), PINMUX_DATA(A20_MARK, PORT39_FN1), PINMUX_DATA(A21_MARK, PORT40_FN1), PINMUX_DATA(A22_MARK, PORT41_FN1), PINMUX_DATA(A23_MARK, PORT42_FN1), PINMUX_DATA(A24_MARK, PORT43_FN1), PINMUX_DATA(A25_MARK, PORT44_FN1), PINMUX_DATA(A26_MARK, PORT45_FN1), PINMUX_DATA(D0_NAF0_MARK, PORT46_FN1), PINMUX_DATA(D1_NAF1_MARK, PORT47_FN1), PINMUX_DATA(D2_NAF2_MARK, PORT48_FN1), PINMUX_DATA(D3_NAF3_MARK, PORT49_FN1), PINMUX_DATA(D4_NAF4_MARK, PORT50_FN1), PINMUX_DATA(D5_NAF5_MARK, PORT51_FN1), PINMUX_DATA(D6_NAF6_MARK, PORT52_FN1), PINMUX_DATA(D7_NAF7_MARK, PORT53_FN1), PINMUX_DATA(D8_NAF8_MARK, PORT54_FN1), PINMUX_DATA(D9_NAF9_MARK, PORT55_FN1), PINMUX_DATA(D10_NAF10_MARK, PORT56_FN1), PINMUX_DATA(D11_NAF11_MARK, PORT57_FN1), PINMUX_DATA(D12_NAF12_MARK, PORT58_FN1), PINMUX_DATA(D13_NAF13_MARK, PORT59_FN1), PINMUX_DATA(D14_NAF14_MARK, PORT60_FN1), PINMUX_DATA(D15_NAF15_MARK, PORT61_FN1), PINMUX_DATA(CS0_MARK, PORT62_FN1), PINMUX_DATA(CS2_MARK, PORT63_FN1), PINMUX_DATA(CS4_MARK, PORT64_FN1), PINMUX_DATA(CS5A_MARK, PORT65_FN1), PINMUX_DATA(CS5B_MARK, PORT66_FN1), PINMUX_DATA(CS6A_MARK, PORT67_FN1), PINMUX_DATA(FCE0_MARK, PORT68_FN1), PINMUX_DATA(RD_FSC_MARK, PORT69_FN1), PINMUX_DATA(WE0_FWE_MARK, PORT70_FN1), PINMUX_DATA(WE1_MARK, PORT71_FN1), PINMUX_DATA(CKO_MARK, PORT72_FN1), PINMUX_DATA(FRB_MARK, PORT73_FN1), PINMUX_DATA(WAIT_MARK, PORT74_FN1), PINMUX_DATA(RDWR_MARK, PORT75_FN1), PINMUX_DATA(MEMC_AD0_MARK, PORT76_FN1), PINMUX_DATA(MEMC_AD1_MARK, PORT77_FN1), PINMUX_DATA(MEMC_AD2_MARK, PORT78_FN1), PINMUX_DATA(MEMC_AD3_MARK, PORT79_FN1), PINMUX_DATA(MEMC_AD4_MARK, PORT80_FN1), PINMUX_DATA(MEMC_AD5_MARK, PORT81_FN1), PINMUX_DATA(MEMC_AD6_MARK, PORT82_FN1), PINMUX_DATA(MEMC_AD7_MARK, PORT83_FN1), PINMUX_DATA(MEMC_AD8_MARK, PORT84_FN1), PINMUX_DATA(MEMC_AD9_MARK, PORT85_FN1), PINMUX_DATA(MEMC_AD10_MARK, PORT86_FN1), PINMUX_DATA(MEMC_AD11_MARK, PORT87_FN1), PINMUX_DATA(MEMC_AD12_MARK, PORT88_FN1), PINMUX_DATA(MEMC_AD13_MARK, PORT89_FN1), PINMUX_DATA(MEMC_AD14_MARK, PORT90_FN1), PINMUX_DATA(MEMC_AD15_MARK, PORT91_FN1), PINMUX_DATA(MEMC_CS0_MARK, PORT92_FN1), PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK, PORT93_FN1), PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK, PORT94_FN1), PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK, PORT95_FN1), PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK, PORT96_FN1), PINMUX_DATA(MEMC_NOE_MARK, PORT97_FN1), PINMUX_DATA(MEMC_NWE_MARK, PORT98_FN1), PINMUX_DATA(MEMC_INT_MARK, PORT99_FN1), PINMUX_DATA(VIO_VD_MARK, PORT100_FN1), PINMUX_DATA(VIO_HD_MARK, PORT101_FN1), PINMUX_DATA(VIO_D0_MARK, PORT102_FN1), PINMUX_DATA(VIO_D1_MARK, PORT103_FN1), PINMUX_DATA(VIO_D2_MARK, PORT104_FN1), PINMUX_DATA(VIO_D3_MARK, PORT105_FN1), PINMUX_DATA(VIO_D4_MARK, PORT106_FN1), PINMUX_DATA(VIO_D5_MARK, PORT107_FN1), PINMUX_DATA(VIO_D6_MARK, PORT108_FN1), PINMUX_DATA(VIO_D7_MARK, PORT109_FN1), PINMUX_DATA(VIO_D8_MARK, PORT110_FN1), PINMUX_DATA(VIO_D9_MARK, PORT111_FN1), PINMUX_DATA(VIO_D10_MARK, PORT112_FN1), PINMUX_DATA(VIO_D11_MARK, PORT113_FN1), PINMUX_DATA(VIO_D12_MARK, PORT114_FN1), PINMUX_DATA(VIO_D13_MARK, PORT115_FN1), PINMUX_DATA(VIO_D14_MARK, PORT116_FN1), PINMUX_DATA(VIO_D15_MARK, PORT117_FN1), PINMUX_DATA(VIO_CLK_MARK, PORT118_FN1), PINMUX_DATA(VIO_FIELD_MARK, PORT119_FN1), PINMUX_DATA(VIO_CKO_MARK, PORT120_FN1), PINMUX_DATA(LCDD0_MARK, PORT121_FN1), PINMUX_DATA(LCDD1_MARK, PORT122_FN1), PINMUX_DATA(LCDD2_MARK, PORT123_FN1), PINMUX_DATA(LCDD3_MARK, PORT124_FN1), PINMUX_DATA(LCDD4_MARK, PORT125_FN1), PINMUX_DATA(LCDD5_MARK, PORT126_FN1), PINMUX_DATA(LCDD6_MARK, PORT127_FN1), PINMUX_DATA(LCDD7_MARK, PORT128_FN1), PINMUX_DATA(LCDD8_MARK, PORT129_FN1), PINMUX_DATA(LCDD9_MARK, PORT130_FN1), PINMUX_DATA(LCDD10_MARK, PORT131_FN1), PINMUX_DATA(LCDD11_MARK, PORT132_FN1), PINMUX_DATA(LCDD12_MARK, PORT133_FN1), PINMUX_DATA(LCDD13_MARK, PORT134_FN1), PINMUX_DATA(LCDD14_MARK, PORT135_FN1), PINMUX_DATA(LCDD15_MARK, PORT136_FN1), PINMUX_DATA(LCDD16_MARK, PORT137_FN1), PINMUX_DATA(LCDD17_MARK, PORT138_FN1), PINMUX_DATA(LCDD18_MARK, PORT139_FN1), PINMUX_DATA(LCDD19_MARK, PORT140_FN1), PINMUX_DATA(LCDD20_MARK, PORT141_FN1), PINMUX_DATA(LCDD21_MARK, PORT142_FN1), PINMUX_DATA(LCDD22_MARK, PORT143_FN1), PINMUX_DATA(LCDD23_MARK, PORT144_FN1), PINMUX_DATA(LCDHSYN_MARK, PORT145_FN1), PINMUX_DATA(LCDVSYN_MARK, PORT146_FN1), PINMUX_DATA(LCDDCK_MARK, PORT147_FN1), PINMUX_DATA(LCDRD_MARK, PORT148_FN1), PINMUX_DATA(LCDDISP_MARK, PORT149_FN1), PINMUX_DATA(LCDLCLK_MARK, PORT150_FN1), PINMUX_DATA(LCDDON_MARK, PORT151_FN1), PINMUX_DATA(SCIFA0_TXD_MARK, PORT152_FN1), PINMUX_DATA(SCIFA0_RXD_MARK, PORT153_FN1), PINMUX_DATA(SCIFA1_TXD_MARK, PORT154_FN1), PINMUX_DATA(SCIFA1_RXD_MARK, PORT155_FN1), PINMUX_DATA(TS_SPSYNC1_MARK, PORT156_FN1), PINMUX_DATA(TS_SDAT1_MARK, PORT157_FN1), PINMUX_DATA(TS_SDEN1_MARK, PORT158_FN1), PINMUX_DATA(TS_SCK1_MARK, PORT159_FN1), PINMUX_DATA(TPU0TO0_MARK, PORT160_FN1), PINMUX_DATA(TPU0TO1_MARK, PORT161_FN1), PINMUX_DATA(SCIFB_SCK_MARK, PORT162_FN1), PINMUX_DATA(SCIFB_RTS_MARK, PORT163_FN1), PINMUX_DATA(SCIFB_CTS_MARK, PORT164_FN1), PINMUX_DATA(SCIFB_TXD_MARK, PORT165_FN1), PINMUX_DATA(SCIFB_RXD_MARK, PORT166_FN1), PINMUX_DATA(VBUS0_0_MARK, PORT167_FN1), PINMUX_DATA(VBUS0_1_MARK, PORT168_FN1), PINMUX_DATA(HDMI_HPD_MARK, PORT169_FN1), PINMUX_DATA(HDMI_CEC_MARK, PORT170_FN1), PINMUX_DATA(SDHICLK0_MARK, PORT171_FN1), PINMUX_DATA(SDHICD0_MARK, PORT172_FN1), PINMUX_DATA(SDHID0_0_MARK, PORT173_FN1), PINMUX_DATA(SDHID0_1_MARK, PORT174_FN1), PINMUX_DATA(SDHID0_2_MARK, PORT175_FN1), PINMUX_DATA(SDHID0_3_MARK, PORT176_FN1), PINMUX_DATA(SDHICMD0_MARK, PORT177_FN1), PINMUX_DATA(SDHIWP0_MARK, PORT178_FN1), PINMUX_DATA(SDHICLK1_MARK, PORT179_FN1), PINMUX_DATA(SDHID1_0_MARK, PORT180_FN1), PINMUX_DATA(SDHID1_1_MARK, PORT181_FN1), PINMUX_DATA(SDHID1_2_MARK, PORT182_FN1), PINMUX_DATA(SDHID1_3_MARK, PORT183_FN1), PINMUX_DATA(SDHICMD1_MARK, PORT184_FN1), PINMUX_DATA(SDHICLK2_MARK, PORT185_FN1), PINMUX_DATA(SDHID2_0_MARK, PORT186_FN1), PINMUX_DATA(SDHID2_1_MARK, PORT187_FN1), PINMUX_DATA(SDHID2_2_MARK, PORT188_FN1), PINMUX_DATA(SDHID2_3_MARK, PORT189_FN1), PINMUX_DATA(SDHICMD2_MARK, PORT190_FN1), /* Function 2 */ PINMUX_DATA(FSIBCK_MARK, PORT4_FN2), PINMUX_DATA(SCIFA4_RXD_MARK, PORT5_FN2), PINMUX_DATA(SCIFA4_TXD_MARK, PORT6_FN2), PINMUX_DATA(SCIFA5_RXD_MARK, PORT8_FN2), PINMUX_DATA(FSIASPDIF_11_MARK, PORT11_FN2), PINMUX_DATA(SCIFA5_TXD_MARK, PORT12_FN2), PINMUX_DATA(FMSIOLR_MARK, PORT13_FN2), PINMUX_DATA(FMSIOBT_MARK, PORT14_FN2), PINMUX_DATA(FSIASPDIF_15_MARK, PORT15_FN2), PINMUX_DATA(FMSIILR_MARK, PORT16_FN2), PINMUX_DATA(FMSIIBT_MARK, PORT17_FN2), PINMUX_DATA(BS_MARK, PORT19_FN2), PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT36_FN2), PINMUX_DATA(MSIOF0_TSCK_MARK, PORT37_FN2), PINMUX_DATA(MSIOF0_RXD_MARK, PORT38_FN2), PINMUX_DATA(MSIOF0_RSCK_MARK, PORT39_FN2), PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT40_FN2), PINMUX_DATA(MSIOF0_MCK0_MARK, PORT41_FN2), PINMUX_DATA(MSIOF0_MCK1_MARK, PORT42_FN2), PINMUX_DATA(MSIOF0_SS1_MARK, PORT43_FN2), PINMUX_DATA(MSIOF0_SS2_MARK, PORT44_FN2), PINMUX_DATA(MSIOF0_TXD_MARK, PORT45_FN2), PINMUX_DATA(FMSICK_MARK, PORT65_FN2), PINMUX_DATA(FCE1_MARK, PORT66_FN2), PINMUX_DATA(BBIF1_RXD_MARK, PORT76_FN2), PINMUX_DATA(BBIF1_TSYNC_MARK, PORT77_FN2), PINMUX_DATA(BBIF1_TSCK_MARK, PORT78_FN2), PINMUX_DATA(BBIF1_TXD_MARK, PORT79_FN2), PINMUX_DATA(BBIF1_RSCK_MARK, PORT80_FN2), PINMUX_DATA(BBIF1_RSYNC_MARK, PORT81_FN2), PINMUX_DATA(BBIF1_FLOW_MARK, PORT82_FN2), PINMUX_DATA(BB_RX_FLOW_N_MARK, PORT83_FN2), PINMUX_DATA(MSIOF1_RSCK_MARK, PORT84_FN2), PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT85_FN2), PINMUX_DATA(MSIOF1_MCK0_MARK, PORT86_FN2), PINMUX_DATA(MSIOF1_MCK1_MARK, PORT87_FN2), PINMUX_DATA(MSIOF1_TSCK_88_MARK, PORT88_FN2, MSEL4CR_10_1), PINMUX_DATA(MSIOF1_TSYNC_89_MARK, PORT89_FN2, MSEL4CR_10_1), PINMUX_DATA(MSIOF1_TXD_90_MARK, PORT90_FN2, MSEL4CR_10_1), PINMUX_DATA(MSIOF1_RXD_91_MARK, PORT91_FN2, MSEL4CR_10_1), PINMUX_DATA(MSIOF1_SS1_92_MARK, PORT92_FN2, MSEL4CR_10_1), PINMUX_DATA(MSIOF1_SS2_93_MARK, PORT93_FN2, MSEL4CR_10_1), PINMUX_DATA(SCIFA2_CTS1_MARK, PORT94_FN2), PINMUX_DATA(SCIFA2_RTS1_MARK, PORT95_FN2), PINMUX_DATA(SCIFA2_TXD1_MARK, PORT96_FN2), PINMUX_DATA(SCIFA2_RXD1_MARK, PORT97_FN2), PINMUX_DATA(SCIFA2_SCK1_MARK, PORT98_FN2), PINMUX_DATA(I2C_SCL2_MARK, PORT110_FN2), PINMUX_DATA(I2C_SDA2_MARK, PORT111_FN2), PINMUX_DATA(I2C_SCL3_MARK, PORT114_FN2, MSEL4CR_16_1), PINMUX_DATA(I2C_SDA3_MARK, PORT115_FN2, MSEL4CR_16_1), PINMUX_DATA(I2C_SCL4_MARK, PORT116_FN2, MSEL4CR_17_1), PINMUX_DATA(I2C_SDA4_MARK, PORT117_FN2, MSEL4CR_17_1), PINMUX_DATA(MSIOF2_RSCK_MARK, PORT134_FN2), PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT135_FN2), PINMUX_DATA(MSIOF2_MCK0_MARK, PORT136_FN2), PINMUX_DATA(MSIOF2_MCK1_MARK, PORT137_FN2), PINMUX_DATA(MSIOF2_SS1_MARK, PORT138_FN2), PINMUX_DATA(MSIOF2_SS2_MARK, PORT139_FN2), PINMUX_DATA(SCIFA3_CTS_140_MARK, PORT140_FN2, MSEL3CR_9_1), PINMUX_DATA(SCIFA3_RTS_141_MARK, PORT141_FN2), PINMUX_DATA(SCIFA3_SCK_MARK, PORT142_FN2), PINMUX_DATA(SCIFA3_TXD_MARK, PORT143_FN2), PINMUX_DATA(SCIFA3_RXD_MARK, PORT144_FN2), PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT148_FN2), PINMUX_DATA(MSIOF2_TSCK_MARK, PORT149_FN2), PINMUX_DATA(MSIOF2_RXD_MARK, PORT150_FN2), PINMUX_DATA(MSIOF2_TXD_MARK, PORT151_FN2), PINMUX_DATA(SCIFA0_SCK_MARK, PORT156_FN2), PINMUX_DATA(SCIFA0_RTS_MARK, PORT157_FN2), PINMUX_DATA(SCIFA0_CTS_MARK, PORT158_FN2), PINMUX_DATA(SCIFA1_SCK_MARK, PORT159_FN2), PINMUX_DATA(SCIFA1_RTS_MARK, PORT160_FN2), PINMUX_DATA(SCIFA1_CTS_MARK, PORT161_FN2), /* Function 3 */ PINMUX_DATA(VIO_CKO1_MARK, PORT16_FN3), PINMUX_DATA(VIO_CKO2_MARK, PORT17_FN3), PINMUX_DATA(IDIN_1_18_MARK, PORT18_FN3, MSEL4CR_14_1), PINMUX_DATA(MSIOF1_TSCK_39_MARK, PORT39_FN3, MSEL4CR_10_0), PINMUX_DATA(MSIOF1_TSYNC_40_MARK, PORT40_FN3, MSEL4CR_10_0), PINMUX_DATA(MSIOF1_TXD_41_MARK, PORT41_FN3, MSEL4CR_10_0), PINMUX_DATA(MSIOF1_RXD_42_MARK, PORT42_FN3, MSEL4CR_10_0), PINMUX_DATA(MSIOF1_SS1_43_MARK, PORT43_FN3, MSEL4CR_10_0), PINMUX_DATA(MSIOF1_SS2_44_MARK, PORT44_FN3, MSEL4CR_10_0), PINMUX_DATA(MMCD1_0_MARK, PORT54_FN3, MSEL4CR_15_1), PINMUX_DATA(MMCD1_1_MARK, PORT55_FN3, MSEL4CR_15_1), PINMUX_DATA(MMCD1_2_MARK, PORT56_FN3, MSEL4CR_15_1), PINMUX_DATA(MMCD1_3_MARK, PORT57_FN3, MSEL4CR_15_1), PINMUX_DATA(MMCD1_4_MARK, PORT58_FN3, MSEL4CR_15_1), PINMUX_DATA(MMCD1_5_MARK, PORT59_FN3, MSEL4CR_15_1), PINMUX_DATA(MMCD1_6_MARK, PORT60_FN3, MSEL4CR_15_1), PINMUX_DATA(MMCD1_7_MARK, PORT61_FN3, MSEL4CR_15_1), PINMUX_DATA(VINT_I_MARK, PORT65_FN3), PINMUX_DATA(MMCCLK1_MARK, PORT66_FN3, MSEL4CR_15_1), PINMUX_DATA(MMCCMD1_MARK, PORT67_FN3, MSEL4CR_15_1), PINMUX_DATA(TPU0TO2_93_MARK, PORT93_FN3), PINMUX_DATA(TPU0TO2_99_MARK, PORT99_FN3), PINMUX_DATA(TPU0TO3_MARK, PORT112_FN3), PINMUX_DATA(IDIN_0_MARK, PORT113_FN3), PINMUX_DATA(EXTLP_0_MARK, PORT114_FN3), PINMUX_DATA(OVCN2_0_MARK, PORT115_FN3), PINMUX_DATA(PWEN_0_MARK, PORT116_FN3), PINMUX_DATA(OVCN_0_MARK, PORT117_FN3), PINMUX_DATA(KEYOUT7_MARK, PORT121_FN3), PINMUX_DATA(KEYOUT6_MARK, PORT122_FN3), PINMUX_DATA(KEYOUT5_MARK, PORT123_FN3), PINMUX_DATA(KEYOUT4_MARK, PORT124_FN3), PINMUX_DATA(KEYOUT3_MARK, PORT125_FN3), PINMUX_DATA(KEYOUT2_MARK, PORT126_FN3), PINMUX_DATA(KEYOUT1_MARK, PORT127_FN3), PINMUX_DATA(KEYOUT0_MARK, PORT128_FN3), PINMUX_DATA(KEYIN7_MARK, PORT129_FN3), PINMUX_DATA(KEYIN6_MARK, PORT130_FN3), PINMUX_DATA(KEYIN5_MARK, PORT131_FN3), PINMUX_DATA(KEYIN4_MARK, PORT132_FN3), PINMUX_DATA(KEYIN3_133_MARK, PORT133_FN3, MSEL4CR_18_0), PINMUX_DATA(KEYIN2_134_MARK, PORT134_FN3, MSEL4CR_18_0), PINMUX_DATA(KEYIN1_135_MARK, PORT135_FN3, MSEL4CR_18_0), PINMUX_DATA(KEYIN0_136_MARK, PORT136_FN3, MSEL4CR_18_0), PINMUX_DATA(TS_SPSYNC2_MARK, PORT137_FN3), PINMUX_DATA(IROUT_139_MARK, PORT139_FN3), PINMUX_DATA(IRDA_OUT_MARK, PORT140_FN3), PINMUX_DATA(IRDA_IN_MARK, PORT141_FN3), PINMUX_DATA(IRDA_FIRSEL_MARK, PORT142_FN3), PINMUX_DATA(TS_SDAT2_MARK, PORT145_FN3),