/* * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h * * Register definitions for IXP4xx chipset. This file contains * register location and bit definitions only. Platform specific * definitions and helper function declarations are in platform.h * and machine-name.h. * * Copyright (C) 2002 Intel Corporation. * Copyright (C) 2003-2004 MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * */ #ifndef _ASM_ARM_IXP4XX_H_ #define _ASM_ARM_IXP4XX_H_ /* * IXP4xx Linux Memory Map: * * Phy Size Virt Description * ========================================================================= * * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM * * 0x48000000 0x04000000 ioremap'd PCI Memory Space * * 0x50000000 0x10000000 ioremap'd EXP BUS * * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals * * 0xC0000000 0x00001000 0xFEF13000 PCI CFG * * 0xC4000000 0x00001000 0xFEF14000 EXP CFG * * 0x60000000 0x00004000 0xFEF15000 QMgr */ /* * Queue Manager */ #define IXP4XX_QMGR_BASE_PHYS 0x60000000 #define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000) #define IXP4XX_QMGR_REGION_SIZE 0x00004000 /* * Peripheral space, including debug UART. Must be section-aligned so that * it can be used with the low-level debug code. */ #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 /* * PCI Config registers */ #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 /* * Expansion BUS Configuration registers */ #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 #define IXP4XX_EXP_CS0_OFFSET 0x00 #define IXP4XX_EXP_CS1_OFFSET 0x04 #define IXP4XX_EXP_CS2_OFFSET 0x08 #define IXP4XX_EXP_CS3_OFFSET 0x0C #define IXP4XX_EXP_CS4_OFFSET 0x10 #define IXP4XX_EXP_CS5_OFFSET 0x14 #define IXP4XX_EXP_CS6_OFFSET 0x18 #define IXP4XX_EXP_CS7_OFFSET 0x1C #define IXP4XX_EXP_CFG0_OFFSET 0x20 #define IXP4XX_EXP_CFG1_OFFSET 0x24 #define IXP4XX_EXP_CFG2_OFFSET 0x28 #define IXP4XX_EXP_CFG3_OFFSET 0x2C /* * Expansion Bus Controller registers. */ #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) /* * Peripheral Space Register Region Base Addresses */ #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) /* ixp46X only */ #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) #define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000) #define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000) #define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000) #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) /* ixp46X only */ #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) /* * Constants to make it easy to access Interrupt Controller registers */ #define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */ #define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */ #define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ #define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */ #define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */ #define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */ #define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ #define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ /* * IXP465-only */ #define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */ #define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */ #define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */ #define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */ #define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */