/* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This contains i.MX27-specific hardware definitions. For those * hardware pieces that are common between i.MX21 and i.MX27, have a * look at mx2x.h. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * MA 02110-1301, USA. */ #ifndef __MACH_MX27_H__ #define __MACH_MX27_H__ #define MX27_AIPI_BASE_ADDR 0x10000000 #define MX27_AIPI_SIZE SZ_1M #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) #define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) #define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) #define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) #define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) #define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) #define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) #define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) #define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) #define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) #define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) #define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) #define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) #define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) #define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) #define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) #define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) #define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) #define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) #define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) #define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) #define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) #define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) #define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) #define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) #define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) #define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) #define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) #define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) #define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) #define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) #define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) #define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) #define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) #define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) #define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) #define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) #define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) #define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) #define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)