/* * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #ifndef _CDEF_BF54X_H #define _CDEF_BF54X_H /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ /* ************************************************************** */ /* PLL Registers */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) /* SIC Registers */ #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2)) #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val) #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2)) #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val) #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) #define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) #define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) #define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) #define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) #define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) /* Watchdog Timer Registers */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) /* RTC Registers */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) /* UART0 Registers */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) #define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) #define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) /* SPI0 Registers */ #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) /* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ /* Two Wire Interface Registers (TWI0) */ /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) /* Asynchronous Memory Control Registers */ #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) #define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL) #define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val) #define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) #define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) #define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL) #define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val) /* DDR Memory Control Registers */ #define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) #define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) #define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) #define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) #define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) #define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val) #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) /* DDR BankRead and Write Count Registers */ #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) #define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) #define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) #define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) #define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) #define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) #define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) #define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) #define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) #define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) #define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) #define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) #define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) #define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) #define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) #define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) #define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) #define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) #define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) #define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) #define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) #define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) #define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) #define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) #define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) /* DMAC0 Registers */ #define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val) #define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) #define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val) /* DMA Channel 0 Registers */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) /* DMA Channel 1 Registers */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) /* DMA Channel 2 Registers */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) /* DMA Channel 3 Registers */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) /* DMA Channel 4 Registers */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) /* DMA Channel 5 Registers */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) /* DMA Channel 6 Registers */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) /* DMA Channel 7 Registers */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) /* DMA Channel 8 Registers */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)