/* include/asm-m68knommu/MC68328.h: '328 control registers * * Copyright (C) 1999 Vladimir Gurevich * Bear & Hare Software, Inc. * * Based on include/asm-m68knommu/MC68332.h * Copyright (C) 1998 Kenneth Albanowski , * */ #ifndef _MC68328_H_ #define _MC68328_H_ #define BYTE_REF(addr) (*((volatile unsigned char*)addr)) #define WORD_REF(addr) (*((volatile unsigned short*)addr)) #define LONG_REF(addr) (*((volatile unsigned long*)addr)) #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) /********** * * 0xFFFFF0xx -- System Control * **********/ /* * System Control Register (SCR) */ #define SCR_ADDR 0xfffff000 #define SCR BYTE_REF(SCR_ADDR) #define SCR_WDTH8 0x01 /* 8-Bit Width Select */ #define SCR_DMAP 0x04 /* Double Map */ #define SCR_SO 0x08 /* Supervisor Only */ #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ #define SCR_PRV 0x20 /* Privilege Violation */ #define SCR_WPV 0x40 /* Write Protect Violation */ #define SCR_BETO 0x80 /* Bus-Error TimeOut */ /* * Mask Revision Register */ #define MRR_ADDR 0xfffff004 #define MRR LONG_REF(MRR_ADDR) /********** * * 0xFFFFF1xx -- Chip-Select logic * **********/ /********** * * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control * **********/ /* * Group Base Address Registers */ #define GRPBASEA_ADDR 0xfffff100 #define GRPBASEB_ADDR 0xfffff102 #define GRPBASEC_ADDR 0xfffff104 #define GRPBASED_ADDR 0xfffff106 #define GRPBASEA WORD_REF(GRPBASEA_ADDR) #define GRPBASEB WORD_REF(GRPBASEB_ADDR) #define GRPBASEC WORD_REF(GRPBASEC_ADDR) #define GRPBASED WORD_REF(GRPBASED_ADDR) #define GRPBASE_V 0x0001 /* Valid */ #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */ /* * Group Base Address Mask Registers */ #define GRPMASKA_ADDR 0xfffff108 #define GRPMASKB_ADDR 0xfffff10a #define GRPMASKC_ADDR 0xfffff10c #define GRPMASKD_ADDR 0xfffff10e #define GRPMASKA WORD_REF(GRPMASKA_ADDR) #define GRPMASKB WORD_REF(GRPMASKB_ADDR) #define GRPMASKC WORD_REF(GRPMASKC_ADDR) #define GRPMASKD WORD_REF(GRPMASKD_ADDR) #define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */ /* * Chip-Select Option Registers (group A) */ #define CSA0_ADDR 0xfffff110 #define CSA1_ADDR 0xfffff114 #define CSA2_ADDR 0xfffff118 #define CSA3_ADDR 0xfffff11c #define CSA0 LONG_REF(CSA0_ADDR) #define CSA1 LONG_REF(CSA1_ADDR) #define CSA2 LONG_REF(CSA2_ADDR) #define CSA3 LONG_REF(CSA3_ADDR) #define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */ #define CSA_WAIT_SHIFT 0 #define CSA_RO 0x00000008 /* Read-Only */ #define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ #define CSA_AM_SHIFT 8 #define CSA_BUSW 0x00010000 /* Bus Width Select */ #define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ #define CSA_AC_SHIFT 24 /* * Chip-Select Option Registers (group B) */ #define CSB0_ADDR 0xfffff120 #define CSB1_ADDR 0xfffff124 #define CSB2_ADDR 0xfffff128 #define CSB3_ADDR 0xfffff12c #define CSB0 LONG_REF(CSB0_ADDR) #define CSB1 LONG_REF(CSB1_ADDR) #define CSB2 LONG_REF(CSB2_ADDR) #define CSB3 LONG_REF(CSB3_ADDR) #define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */ #define CSB_WAIT_SHIFT 0 #define CSB_RO 0x00000008 /* Read-Only */ #define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ #define CSB_AM_SHIFT 8 #define CSB_BUSW 0x00010000 /* Bus Width Select */ #define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ #define CSB_AC_SHIFT 24 /* * Chip-Select Option Registers (group C) */ #define CSC0_ADDR 0xfffff130 #define CSC1_ADDR 0xfffff134 #define CSC2_ADDR 0xfffff138 #define CSC3_ADDR 0xfffff13c #define CSC0 LONG_REF(CSC0_ADDR) #define CSC1 LONG_REF(CSC1_ADDR) #define CSC2 LONG_REF(CSC2_ADDR) #define CSC3 LONG_REF(CSC3_ADDR) #define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */ #define CSC_WAIT_SHIFT 0 #define CSC_RO 0x00000008 /* Read-Only */ #define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ #define CSC_AM_SHIFT 4 #define CSC_BUSW 0x00010000 /* Bus Width Select */ #define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ #define CSC_AC_SHIFT 20 /* * Chip-Select Option Registers (group D) */ #define CSD0_ADDR 0xfffff140 #define CSD1_ADDR 0xfffff144 #define CSD2_ADDR 0xfffff148 #define CSD3_ADDR 0xfffff14c #define CSD0 LONG_REF(CSD0_ADDR) #define CSD1 LONG_REF(CSD1_ADDR) #define CSD2 LONG_REF(CSD2_ADDR) #define CSD3 LONG_REF(CSD3_ADDR) #define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */ #define CSD_WAIT_SHIFT 0 #define CSD_RO 0x00000008 /* Read-Only */ #define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ #define CSD_AM_SHIFT 4 #define CSD_BUSW 0x00010000 /* Bus Width Select */ #define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */