/****************************************************************************/ /* * m532xsim.h -- ColdFire 5329 registers */ /****************************************************************************/ #ifndef m532xsim_h #define m532xsim_h /****************************************************************************/ #define CPU_NAME "COLDFIRE(m532x)" #define CPU_INSTR_PER_JIFFY 3 #define MCF_BUSCLK (MCF_CLK / 3) #include #define MCFINT_VECBASE 64 #define MCFINT_UART0 26 /* Interrupt number for UART0 */ #define MCFINT_UART1 27 /* Interrupt number for UART1 */ #define MCFINT_UART2 28 /* Interrupt number for UART2 */ #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ #define MCFINT_FECRX0 36 /* Interrupt number for FEC */ #define MCFINT_FECTX0 40 /* Interrupt number for FEC */ #define MCFINT_FECENTC0 42 /* Interrupt number for FEC */ #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) #define MCF_WTM_WCR 0xFC098000 /* * Define the 532x SIM register set addresses. */ #define MCFSIM_IPRL 0xFC048004 #define MCFSIM_IPRH 0xFC048000 #define MCFSIM_IPR MCFSIM_IPRL #define MCFSIM_IMRL 0xFC04800C #define MCFSIM_IMRH 0xFC048008 #define MCFSIM_IMR MCFSIM_IMRL #define MCFSIM_ICR0 0xFC048040 #define MCFSIM_ICR1 0xFC048041 #define MCFSIM_ICR2 0xFC048042 #define MCFSIM_ICR3 0xFC048043 #define MCFSIM_ICR4 0xFC048044 #define MCFSIM_ICR5 0xFC048045 #define MCFSIM_ICR6 0xFC048046 #define MCFSIM_ICR7 0xFC048047 #define MCFSIM_ICR8 0xFC048048 #define MCFSIM_ICR9 0xFC048049 #define MCFSIM_ICR10 0xFC04804A #define MCFSIM_ICR11 0xFC04804B /* * Some symbol defines for the above... */ #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ #define MCFINTC0_SIMR 0xFC04801C #define MCFINTC0_CIMR 0xFC04801D #define MCFINTC0_ICR0 0xFC048040 #define MCFINTC1_SIMR 0xFC04C01C #define MCFINTC1_CIMR 0xFC04C01D #define MCFINTC1_ICR0 0xFC04C040 #define MCFINTC2_SIMR (0) #define MCFINTC2_CIMR (0) #define MCFINTC2_ICR0 (0) #define MCFSIM_ICR_TIMER1 (0xFC048040+32) #define MCFSIM_ICR_TIMER2 (0xFC048040+33) /* * Define system peripheral IRQ usage. */ #define MCF_IRQ_TIMER (64 + 32) /* Timer0 */ #define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */ /* * UART module. */ #define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */ #define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */ #define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */ /* * FEC module. */ #define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */ #define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */ /* * QSPI module. */ #define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */ #define MCFQSPI_SIZE 0x40 /* Size of QSPI region */ #define MCFQSPI_CS0 84 #define MCFQSPI_CS1 85 #define MCFQSPI_CS2 86 /* * Timer module. */ #define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */ #define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */ #define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */ #define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */ /********************************************************************* * * Reset Controller Module * *********************************************************************/ #define MCF_RCR 0xFC0A0000 #define MCF_RSR 0xFC0A0001 #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ /* * Power Management */ #define MCFPM_WCR 0xfc040013 #define MCFPM_PPMSR0 0xfc04002c #define MCFPM_PPMCR0 0xfc04002d #define MCFPM_PPMSR1 0xfc04002e #define MCFPM_PPMCR1 0xfc04002f #define MCFPM_PPMHR0 0xfc040030 #define MCFPM_PPMLR0 0xfc040034 #define MCFPM_PPMHR1 0xfc040038 #define MCFPM_LPCR 0xec090007 /* * The M5329EVB board needs a help getting its devices initialized * at kernel start time if dBUG doesn't set it up (for example * it is not used), so we need to do it manually. */ #ifdef __ASSEMBLER__ .macro m5329EVB_setup movel #0xFC098000, %a7 movel #0x0, (%a7) #define CORE_SRAM 0x80000000 #define CORE_SRAM_SIZE 0x8000 movel #CORE_SRAM, %d0 addl #0x221, %d0 movec %d0,%RAMBAR1 movel #CORE_SRAM, %sp addl #CORE_SRAM_SIZE, %sp jsr sysinit .endm #define PLATFORM_SETUP m5329EVB_setup #endif /* __ASSEMBLER__ */ /********************************************************************* * * Chip Configuration Module (CCM) * *********************************************************************/ /* Register read/write macros */ #define MCF_CCM_CCR 0xFC0A0004 #define MCF_CCM_RCON 0xFC0A0008 #define MCF_CCM_CIR 0xFC0A000A #define MCF_CCM_MISCCR 0xFC0A0010 #define MCF_CCM_CDR 0xFC0A0012 #define MCF_CCM_UHCSR 0xFC0A0014 #define MCF_CCM_UOCSR 0xFC0A0016 /* Bit definitions and macros for MCF_CCM_CCR */ #define MCF_CCM_CCR_RESERVED (0x0001) #define MCF_CCM_CCR_PLL_MODE (0x0003) #define MCF_CCM_CCR_OSC_MODE (0x0005) #define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) #define MCF_CCM_CCR_LOAD (0x0021) #define MCF_CCM_CCR_LIMP (0x0041) #define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) /* Bit definitions and macros for MCF_CCM_RCON */ #define MCF_CCM_RCON_RESERVED (0x0001) #define MCF_CCM_RCON_PLL_MODE (0x0003) #define MCF_CCM_RCON_OSC_MODE (0x0005) #define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) #define MCF_CCM_RCON_LOAD (0x0021) #define MCF_CCM_RCON_LIMP (0x0041) #define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) /* Bit definitions and macros for MCF_CCM_CIR */ #define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) #define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Bit definitions and macros for MCF_CCM_MISCCR */ #define MCF_CCM_MISCCR_USBSRC (0x0001) #define MCF_CCM_MISCCR_USBDIV (0x0002) #define MCF_CCM_MISCCR_SSI_SRC (0x0010) #define MCF_CCM_MISCCR_TIM_DMA (0x0020) #define MCF_CCM_MISCCR_SSI_PUS (0x0040) #define MCF_CCM_MISCCR_SSI_PUE (0x0080) #define MCF_CCM_MISCCR_LCD_CHEN (0x0100) #define MCF_CCM_MISCCR_LIMP (0x1000) #define MCF_CCM_MISCCR_PLL_LOCK (0x2000) /* Bit definitions and macros for MCF_CCM_CDR */ #define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0) #define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Bit definitions and macros for MCF_CCM_UHCSR */ #define MCF_CCM_UHCSR_XPDE (0x0001) #define MCF_CCM_UHCSR_UHMIE (0x0002) #define MCF_CCM_UHCSR_WKUP (0x0004) #define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) /* Bit definitions and macros for MCF_CCM_UOCSR */ #define MCF_CCM_UOCSR_XPDE (0x0001) #define MCF_CCM_UOCSR_UOMIE (0x0002) #define MCF_CCM_UOCSR_WKUP (0x0004) #define MCF_CCM_UOCSR_PWRFLT (0x0008) #define MCF_CCM_UOCSR_SEND (0x0010) #define MCF_CCM_UOCSR_VVLD (0x0020) #define MCF_CCM_UOCSR_BVLD (0x0040) #define MCF_CCM_UOCSR_AVLD (0x0080) #define MCF_CCM_UOCSR_DPPU (0x0100) #define MCF_CCM_UOCSR_DCR_VBUS (0x0200) #define MCF_CCM_UOCSR_CRG_VBUS (0x0400) #define MCF_CCM_UOCSR_DRV_VBUS (0x0800) #define MCF_CCM_UOCSR_DMPD (0x1000) #define MCF_CCM_UOCSR_DPPD (0x2000) #define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) /********************************************************************* * * FlexBus Chip Selects (FBCS) * *********************************************************************/ /* Register read/write macros */ #define MCF_FBCS0_CSAR 0xFC008000