/* * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions * * Copyright (C) 2005-2009 Texas Instruments, Inc. * Copyright (C) 2004-2009 Nokia Corporation * * Richard Woodruff * * The OMAP2 processor can be run at several discrete 'PRCM configurations'. * These configurations are characterized by voltage and speed for clocks. * The device is only validated for certain combinations. One way to express * these combinations is via the 'ratio's' which the clocks operate with * respect to each other. These ratio sets are for a given voltage/DPLL * setting. All configurations can be described by a DPLL setting and a ratio * There are 3 ratio sets for the 2430 and X ratio sets for 2420. * * 2430 differs from 2420 in that there are no more phase synchronizers used. * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs * 2430 (iva2.1, NOdsp, mdm) * * XXX Missing voltage data. * * THe format described in this file is deprecated. Once a reasonable * OPP API exists, the data in this file should be converted to use it. * * This is technically part of the OMAP2xxx clock code. */ #ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H #define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H /** * struct prcm_config - define clock rates on a per-OPP basis (24xx) * * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM * * This is deprecated. As soon as we have a decent OPP API, we should * move all this stuff to it. */ struct prcm_config { unsigned long xtal_speed; /* crystal rate */ unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ unsigned long mpu_speed; /* speed of MPU */ unsigned long cm_clksel_mpu; /* mpu divider */ unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ unsigned long cm_clksel_gfx; /* gfx dividers */ unsigned long cm_clksel1_core; /* major subsystem dividers */ unsigned long cm_clksel1_pll; /* m,n */ unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ unsigned long base_sdrc_rfr; /* base refresh timing for a set */ unsigned short flags; }; /* Core fields for cm_clksel, not ratio governed */ #define RX_CLKSEL_DSS1 (0x10 << 8) #define RX_CLKSEL_DSS2 (0x0 << 13) #define RX_CLKSEL_SSI (0x5 << 20) /*------------------------------------------------------------------------- * Voltage/DPLL ratios *-------------------------------------------------------------------------*/ /* 2430 Ratio's, 2430-Ratio Config 1 */ #define R1_CLKSEL_L3 (4 << 0) #define R1_CLKSEL_L4 (2 << 5) #define R1_CLKSEL_USB (4 << 25) #define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ R1_CLKSEL_L4 | R1_CLKSEL_L3) #define R1_CLKSEL_MPU (2 << 0) #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU #define R1_CLKSEL_DSP (2 << 0) #define R1_CLKSEL_DSP_IF (2 << 5) #define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) #define R1_CLKSEL_GFX (2 << 0) #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX #define R1_CLKSEL_MDM (4 << 0) #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM /* 2430-Ratio Config 2 */ #define R2_CLKSEL_L3 (6 << 0) #define R2_CLKSEL_L4 (2 << 5) #define R2_CLKSEL_USB (2 << 25) #define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ R2_CLKSEL_L4 | R2_CLKSEL_L3) #define R2_CLKSEL_MPU (2 << 0) #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU #define R2_CLKSEL_DSP (2 << 0) #define R2_CLKSEL_DSP_IF (3 << 5) #define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) #define R2_CLKSEL_GFX (2 << 0) #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX #define R2_CLKSEL_MDM (6 << 0) #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM /* 2430-Ratio Bootm (BYPASS) */ #define RB_CLKSEL_L3 (1 << 0) #define RB_CLKSEL_L4 (1 << 5) #define RB_CLKSEL_USB (1 << 25) #define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ RB_CLKSEL_L4 | RB_CLKSEL_L3) #define RB_CLKSEL_MPU (1 << 0) #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU #define RB_CLKSEL_DSP (1 << 0) #define RB_CLKSEL_DSP_IF (1 << 5) #define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) #define RB_CLKSEL_GFX (1 << 0) #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX #define RB_CLKSEL_MDM (1 << 0) #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM /* 2420 Ratio Equivalents */ #define RXX_CLKSEL_VLYNQ (0x12 << 15) #define RXX_CLKSEL_SSI (0x8 << 20) /* 2420-PRCM III 532MHz core */ #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ #define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ RIII_CLKSEL_L3) #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ #define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ RIII_CLKSEL_DSP) #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX /* 2420-PRCM II 600MHz core */ #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ #define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \