/* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /************************************************************************** * * Copyright © ARM Limited 1998. All rights reserved. * ***********************************************************************/ /* ************************************************************************ * * Integrator address map * * ***********************************************************************/ #ifndef __address_h #define __address_h 1 /* ======================================================================== * Integrator definitions * ======================================================================== * ------------------------------------------------------------------------ * Memory definitions * ------------------------------------------------------------------------ * Integrator memory map * */ #define INTEGRATOR_BOOT_ROM_LO 0x00000000 #define INTEGRATOR_BOOT_ROM_HI 0x20000000 #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K /* * New Core Modules have different amounts of SSRAM, the amount of SSRAM * fitted can be found in HDR_STAT. * * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to * the minimum amount of SSRAM fitted on any core module. * * New Core Modules also alias the SSRAM. * */ #define INTEGRATOR_SSRAM_BASE 0x00000000 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 #define INTEGRATOR_SSRAM_SIZE SZ_256K #define INTEGRATOR_FLASH_BASE 0x24000000 #define INTEGRATOR_FLASH_SIZE SZ_32M #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K /* * SDRAM is a SIMM therefore the size is not known. * */ #define INTEGRATOR_SDRAM_BASE 0x00040000 #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 /* * Logic expansion modules * */ #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 /* ------------------------------------------------------------------------ * Integrator header card registers * ------------------------------------------------------------------------ * */ #define INTEGRATOR_HDR_ID_OFFSET 0x00 #define INTEGRATOR_HDR_PROC_OFFSET 0x04 #define INTEGRATOR_HDR_OSC_OFFSET 0x08 #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C #define INTEGRATOR_HDR_STAT_OFFSET 0x10 #define INTEGRATOR_HDR_LOCK_OFFSET 0x14 #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 #define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ #define INTEGRATOR_HDR_IC_OFFSET 0x40 #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 #define INTEGRATOR_HDR_BASE 0x10000000 #define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) #define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) #define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) #define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) #define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) #define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) #define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) #define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) #define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) #define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) #define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) #define INTEGRATOR_HDR_CTRL_LED 0x01 #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 #define INTEGRATOR_HDR_CTRL_REMAP 0x04 #define INTEGRATOR_HDR_CTRL_RESET 0x08 #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 #define INTEGRATOR_HDR_CTRL_SYNC 0x80 #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) /* ------------------------------------------------------------------------ * Integrator system registers * ------------------------------------------------------------------------ * */ /* * System Controller