/* * AM33XX CM offset macros * * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ * Vaibhav Hiremath * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H #include #include #include #include #include "common.h" #include "cm.h" #include "cm-regbits-33xx.h" #include "cm33xx.h" /* CM base address */ #define AM33XX_CM_BASE 0x44e00000 #define AM33XX_CM_REGADDR(inst, reg) \ AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) /* CM instances */ #define AM33XX_CM_PER_MOD 0x0000 #define AM33XX_CM_WKUP_MOD 0x0400 #define AM33XX_CM_DPLL_MOD 0x0500 #define AM33XX_CM_MPU_MOD 0x0600 #define AM33XX_CM_DEVICE_MOD 0x0700 #define AM33XX_CM_RTC_MOD 0x0800 #define AM33XX_CM_GFX_MOD 0x0900 #define AM33XX_CM_CEFUSE_MOD 0x0A00 /* CM */ /* CM.PER_CM register offsets */ #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004 #define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008 #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 #define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 #define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c #define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 #define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 #define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c #define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 #define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 #define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 #define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c #define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 #define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 #define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 #define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c #define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 #define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 #define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 #define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 #define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 #define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 #define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c #define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 #define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)