/* linux/arch/arm/plat-samsung/devs.c * * Copyright (c) 2011 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Base SAMSUNG platform device definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); /* AC97 */ #ifdef CONFIG_CPU_S3C2440 static struct resource s3c_ac97_resource[] = { [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97), [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97), [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"), [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"), [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"), }; struct platform_device s3c_device_ac97 = { .name = "samsung-ac97", .id = -1, .num_resources = ARRAY_SIZE(s3c_ac97_resource), .resource = s3c_ac97_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; #endif /* CONFIG_CPU_S3C2440 */ /* ADC */ #ifdef CONFIG_PLAT_S3C24XX static struct resource s3c_adc_resource[] = { [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC), [1] = DEFINE_RES_IRQ(IRQ_TC), [2] = DEFINE_RES_IRQ(IRQ_ADC), }; struct platform_device s3c_device_adc = { .name = "s3c24xx-adc", .id = -1, .num_resources = ARRAY_SIZE(s3c_adc_resource), .resource = s3c_adc_resource, }; #endif /* CONFIG_PLAT_S3C24XX */ #if defined(CONFIG_SAMSUNG_DEV_ADC) static struct resource s3c_adc_resource[] = { [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256), [1] = DEFINE_RES_IRQ(IRQ_TC), [2] = DEFINE_RES_IRQ(IRQ_ADC), }; struct platform_device s3c_device_adc = { .name = "samsung-adc", .id = -1, .num_resources = ARRAY_SIZE(s3c_adc_resource), .resource = s3c_adc_resource, }; #endif /* CONFIG_SAMSUNG_DEV_ADC */ /* Camif Controller */ #ifdef CONFIG_CPU_S3C2440 static struct resource s3c_camif_resource[] = { [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF), [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C), [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P), }; struct platform_device s3c_device_camif = { .name = "s3c2440-camif", .id = -1, .num_resources = ARRAY_SIZE(s3c_camif_resource), .resource = s3c_camif_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; #endif /* CONFIG_CPU_S3C2440 */ /* ASOC DMA */ struct platform_device samsung_asoc_idma = { .name = "samsung-idma", .id = -1, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; /* FB */ #ifdef CONFIG_S3C_DEV_FB static struct resource s3c_fb_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K), [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC), [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO), [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM), }; struct platform_device s3c_device_fb = { .name = "s3c-fb", .id = -1, .num_resources = ARRAY_SIZE(s3c_fb_resource), .resource = s3c_fb_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) { s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), &s3c_device_fb); } #endif /* CONFIG_S3C_DEV_FB */ /* FIMC */ #ifdef CONFIG_S5P_DEV_FIMC0 static struct resource s5p_fimc0_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_FIMC0), }; struct platform_device s5p_device_fimc0 = { .name = "s5p-fimc", .id = 0, .num_resources = ARRAY_SIZE(s5p_fimc0_resource), .resource = s5p_fimc0_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; struct platform_device s5p_device_fimc_md = { .name = "s5p-fimc-md", .id = -1, }; #endif /* CONFIG_S5P_DEV_FIMC0 */ #ifdef CONFIG_S5P_DEV_FIMC1 static struct resource s5p_fimc1_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_FIMC1), }; struct platform_device s5p_device_fimc1 = { .name = "s5p-fimc", .id = 1, .num_resources = ARRAY_SIZE(s5p_fimc1_resource), .resource = s5p_fimc1_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_FIMC1 */ #ifdef CONFIG_S5P_DEV_FIMC2 static struct resource s5p_fimc2_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_FIMC2), }; struct platform_device s5p_device_fimc2 = { .name = "s5p-fimc", .id = 2, .num_resources = ARRAY_SIZE(s5p_fimc2_resource), .resource = s5p_fimc2_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_FIMC2 */ #ifdef CONFIG_S5P_DEV_FIMC3 static struct resource s5p_fimc3_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_FIMC3), }; struct platform_device s5p_device_fimc3 = { .name = "s5p-fimc", .id = 3, .num_resources = ARRAY_SIZE(s5p_fimc3_resource), .resource = s5p_fimc3_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_FIMC3 */ /* G2D */ #ifdef CONFIG_S5P_DEV_G2D static struct resource s5p_g2d_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_2D), }; struct platform_device s5p_device_g2d = { .name = "s5p-g2d", .id = 0, .num_resources = ARRAY_SIZE(s5p_g2d_resource), .resource = s5p_g2d_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_G2D */ #ifdef CONFIG_S5P_DEV_JPEG static struct resource s5p_jpeg_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_JPEG), }; struct platform_device s5p_device_jpeg = { .name = "s5p-jpeg", .id = 0, .num_resources = ARRAY_SIZE(s5p_jpeg_resource), .resource = s5p_jpeg_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_JPEG */ /* FIMD0 */ #ifdef CONFIG_S5P_DEV_FIMD0 static struct resource s5p_fimd0_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K), [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC), [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO), [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM), }; struct platform_device s5p_device_fimd0 = { .name = "s5p-fb", .id = 0, .num_resources = ARRAY_SIZE(s5p_fimd0_resource), .resource = s5p_fimd0_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd) { s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), &s5p_device_fimd0); } #endif /* CONFIG_S5P_DEV_FIMD0 */ /* HWMON */ #ifdef CONFIG_S3C_DEV_HWMON struct platform_device s3c_device_hwmon = { .name = "s3c-hwmon", .id = -1, .dev.parent = &s3c_device_adc.dev, }; void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd) { s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata), &s3c_device_hwmon); } #endif /* CONFIG_S3C_DEV_HWMON */ /* HSMMC */ #ifdef CONFIG_S3C_DEV_HSMMC static struct resource s3c_hsmmc_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_HSMMC0), }; struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), }; struct platform_device s3c_device_hsmmc0 = { .name = "s3c-sdhci", .id = 0, .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), .resource = s3c_hsmmc_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &s3c_hsmmc0_def_platdata, }, }; void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) { s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata); } #endif /* CONFIG_S3C_DEV_HSMMC */ #ifdef CONFIG_S3C_DEV_HSMMC1 static struct resource s3c_hsmmc1_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_HSMMC1), }; struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), }; struct platform_device s3c_device_hsmmc1 = { .name = "s3c-sdhci", .id = 1, .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource), .resource = s3c_hsmmc1_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &s3c_hsmmc1_def_platdata, }, }; void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) { s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata); } #endif /* CONFIG_S3C_DEV_HSMMC1 */ /* HSMMC2 */ #ifdef CONFIG_S3C_DEV_HSMMC2 static struct resource s3c_hsmmc2_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_HSMMC2), }; struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), }; struct platform_device s3c_device_hsmmc2 = { .name = "s3c-sdhci", .id = 2, .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource), .resource = s3c_hsmmc2_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &s3c_hsmmc2_def_platdata, }, }; void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) { s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata); } #endif /* CONFIG_S3C_DEV_HSMMC2 */ #ifdef CONFIG_S3C_DEV_HSMMC3 static struct resource s3c_hsmmc3_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_HSMMC3), }; struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), }; struct platform_device s3c_device_hsmmc3 = { .name = "s3c-sdhci", .id = 3, .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource), .resource = s3c_hsmmc3_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &s3c_hsmmc3_def_platdata, }, }; void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd) { s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata); } #endif /* CONFIG_S3C_DEV_HSMMC3 */ /* I2C */ static struct resource s3c_i2c0_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC), }; struct platform_device s3c_device_i2c0 = { .name = "s3c2410-i2c", .id = 0, .num_resources = ARRAY_SIZE(s3c_i2c0_resource), .resource = s3c_i2c0_resource, }; struct s3c2410_platform_i2c default_i2c_data __initdata = { .flags = 0, .slave_addr = 0x10, .frequency = 100*1000, .sda_delay = 100, }; void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; pd->bus_num = 0; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s3c_device_i2c0); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c0_cfg_gpio; } #ifdef CONFIG_S3C_DEV_I2C1 static struct resource s3c_i2c1_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC1), }; struct platform_device s3c_device_i2c1 = { .name = "s3c2410-i2c", .id = 1, .num_resources = ARRAY_SIZE(s3c_i2c1_resource), .resource = s3c_i2c1_resource, }; void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; pd->bus_num = 1; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s3c_device_i2c1); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c1_cfg_gpio; } #endif /* CONFIG_S3C_DEV_I2C1 */ #ifdef CONFIG_S3C_DEV_I2C2 static struct resource s3c_i2c2_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC2), }; struct platform_device s3c_device_i2c2 = { .name = "s3c2410-i2c", .id = 2, .num_resources = ARRAY_SIZE(s3c_i2c2_resource), .resource = s3c_i2c2_resource, }; void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; pd->bus_num = 2; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s3c_device_i2c2); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c2_cfg_gpio; } #endif /* CONFIG_S3C_DEV_I2C2 */ #ifdef CONFIG_S3C_DEV_I2C3 static struct resource s3c_i2c3_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC3), }; struct platform_device s3c_device_i2c3 = { .name = "s3c2440-i2c", .id = 3, .num_resources = ARRAY_SIZE(s3c_i2c3_resource), .resource = s3c_i2c3_resource, }; void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; pd->bus_num = 3; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s3c_device_i2c3); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c3_cfg_gpio; } #endif /*CONFIG_S3C_DEV_I2C3 */ #ifdef CONFIG_S3C_DEV_I2C4 static struct resource s3c_i2c4_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC4), }; struct platform_device s3c_device_i2c4 = { .name = "s3c2440-i2c", .id = 4, .num_resources = ARRAY_SIZE(s3c_i2c4_resource), .resource = s3c_i2c4_resource, }; void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; pd->bus_num = 4; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s3c_device_i2c4); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c4_cfg_gpio; } #endif /*CONFIG_S3C_DEV_I2C4 */ #ifdef CONFIG_S3C_DEV_I2C5 static struct resource s3c_i2c5_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC5), }; struct platform_device s3c_device_i2c5 = { .name = "s3c2440-i2c", .id = 5, .num_resources = ARRAY_SIZE(s3c_i2c5_resource), .resource = s3c_i2c5_resource, }; void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; pd->bus_num = 5; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s3c_device_i2c5); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c5_cfg_gpio; } #endif /*CONFIG_S3C_DEV_I2C5 */ #ifdef CONFIG_S3C_DEV_I2C6 static struct resource s3c_i2c6_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC6), }; struct platform_device s3c_device_i2c6 = { .name = "s3c2440-i2c", .id = 6, .num_resources = ARRAY_SIZE(s3c_i2c6_resource), .resource = s3c_i2c6_resource, }; void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; pd->bus_num = 6; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s3c_device_i2c6); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c6_cfg_gpio; } #endif /* CONFIG_S3C_DEV_I2C6 */ #ifdef CONFIG_S3C_DEV_I2C7 static struct resource s3c_i2c7_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC7), }; struct platform_device s3c_device_i2c7 = { .name = "s3c2440-i2c", .id = 7, .num_resources = ARRAY_SIZE(s3c_i2c7_resource), .resource = s3c_i2c7_resource, }; void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; pd->bus_num = 7; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s3c_device_i2c7); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c7_cfg_gpio; } #endif /* CONFIG_S3C_DEV_I2C7 */ /* I2C HDMIPHY */ #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY static struct resource s5p_i2c_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY), }; struct platform_device s5p_device_i2c_hdmiphy = { .name = "s3c2440-hdmiphy-i2c", .id = -1, .num_resources = ARRAY_SIZE(s5p_i2c_resource), .resource = s5p_i2c_resource, }; void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) { struct s3c2410_platform_i2c *npd; if (!pd) { pd = &default_i2c_data; if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412()) pd->bus_num = 8; else if (soc_is_s5pv210()) pd->bus_num = 3; else pd->bus_num = 0; } npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), &s5p_device_i2c_hdmiphy); } static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata; void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info, struct i2c_board_info *mhl_info, int mhl_bus) { struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata; if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412()) pd->hdmiphy_bus = 8; else if (soc_is_s5pv210()) pd->hdmiphy_bus = 3; else pd->hdmiphy_bus = 0; pd->hdmiphy_info = hdmiphy_info; pd->mhl_info = mhl_info; pd->mhl_bus = mhl_bus; s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data), &s5p_device_hdmi); } #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */ /* I2S */ #ifdef CONFIG_PLAT_S3C24XX static struct resource s3c_iis_resource[] = { [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS), }; struct platform_device s3c_device_iis = { .name = "s3c24xx-iis", .id = -1, .num_resources = ARRAY_SIZE(s3c_iis_resource), .resource = s3c_iis_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; #endif /* CONFIG_PLAT_S3C24XX */ /* IDE CFCON */ #ifdef CONFIG_SAMSUNG_DEV_IDE static struct resource s3c_cfcon_resource[] = { [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K), [1] = DEFINE_RES_IRQ(IRQ_CFCON), }; struct platform_device s3c_device_cfcon = { .id = 0, .num_resources = ARRAY_SIZE(s3c_cfcon_resource), .resource = s3c_cfcon_resource, }; void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata) { s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata), &s3c_device_cfcon); } #endif /* CONFIG_SAMSUNG_DEV_IDE */ /* KEYPAD */ #ifdef CONFIG_SAMSUNG_DEV_KEYPAD static struct resource samsung_keypad_resources[] = { [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32), [1] = DEFINE_RES_IRQ(IRQ_KEYPAD), }; struct platform_device samsung_device_keypad = { .name = "samsung-keypad", .id = -1, .num_resources = ARRAY_SIZE(samsung_keypad_resources), .resource = samsung_keypad_resources, }; void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd) { struct samsung_keypad_platdata *npd; npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata), &samsung_device_keypad); if (!npd->cfg_gpio) npd->cfg_gpio = samsung_keypad_cfg_gpio; } #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */ /* LCD Controller */ #ifdef CONFIG_PLAT_S3C24XX static struct resource s3c_lcd_resource[] = { [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD), [1] = DEFINE_RES_IRQ(IRQ_LCD), }; struct platform_device s3c_device_lcd = { .name = "s3c2410-lcd", .id = -1, .num_resources = ARRAY_SIZE(s3c_lcd_resource), .resource = s3c_lcd_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) { struct s3c2410fb_mach_info *npd; npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd); if (npd) { npd->displays = kmemdup(pd->displays, sizeof(struct s3c2410fb_display) * npd->num_displays, GFP_KERNEL); if (!npd->displays) printk(KERN_ERR "no memory for LCD display data\n"); } else { printk(KERN_ERR "no memory for LCD platform data\n"); } } #endif /* CONFIG_PLAT_S3C24XX */ /* MFC */ #ifdef CONFIG_S5P_DEV_MFC static struct resource s5p_mfc_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), [1] = DEFINE_RES_IRQ(IRQ_MFC), }; struct platform_device s5p_device_mfc = { .name = "s5p-mfc", .id = -1,