#include #include #include #include #include #include #include #include "clk.h" #include "common.h" #include "hardware.h" #define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) /* Register offsets */ #define CCM_CSCR IO_ADDR_CCM(0x0) #define CCM_MPCTL0 IO_ADDR_CCM(0x4) #define CCM_MPCTL1 IO_ADDR_CCM(0x8) #define CCM_SPCTL0 IO_ADDR_CCM(0xc) #define CCM_SPCTL1 IO_ADDR_CCM(0x10) #define CCM_OSC26MCTL IO_ADDR_CCM(0x14) #define CCM_PCDR0 IO_ADDR_CCM(0x18) #define CCM_PCDR1 IO_ADDR_CCM(0x1c) #define CCM_PCCR0 IO_ADDR_CCM(0x20) #define CCM_PCCR1 IO_ADDR_CCM(0x24) #define CCM_CCSR IO_ADDR_CCM(0x28) #define CCM_PMCTL IO_ADDR_CCM(0x2c) #define CCM_PMCOUNT IO_ADDR_CCM(0x30) #define CCM_WKGDCTL IO_ADDR_CCM(0x34) #define CCM_CSCR_UPDATE_DIS (1 << 31) #define CCM_CSCR_SSI2 (1 << 23) #define CCM_CSCR_SSI1 (1 << 22) #define CCM_CSCR_VPU (1 << 21) #define CCM_CSCR_MSHC (1 << 20) #define CCM_CSCR_SPLLRES (1 << 19) #define CCM_CSCR_MPLLRES (1 << 18) #define CCM_CSCR_SP (1 << 17) #define CCM_CSCR_MCU (1 << 16) #define CCM_CSCR_OSC26MDIV (1 << 4) #define CCM_CSCR_OSC26M (1 << 3) #define CCM_CSCR_FPM (1 << 2) #define CCM_CSCR_SPEN (1 << 1) #define CCM_CSCR_MPEN (1 << 0) /* i.MX27 TO 2+ */ #define CCM_CSCR_ARM_SRC (1 << 15) #define CCM_SPCTL1_LF (1 << 15) #define CCM_SPCTL1_BRMO (1 << 6) static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", }; static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", }; static const char *clko_sel_clks[] = { "ckil", "fpm", "ckih", "ckih", "ckih", "mpll", "spll", "cpu_div", "ahb", "ipg", "per1_div", "per2_div", "per3_div", "per4_div", "ssi1_div", "ssi2_div", "nfc_div", "mshc_div", "vpu_div", "60m", "32k", "usb_div", "dptc", }; static const char *ssi_sel_clks[] = { "spll", "mpll", }; enum mx27_clks { dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div, clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate, sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate, rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate, kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate, gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate, gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate, emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate, vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate, usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate, vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate, csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, mpll_sel, clk_max }; static struct clk *clk[clk_max]; int __init mx27_clocks_init(unsigned long fref) { int i; clk[dummy] = imx_clk_fixed("dummy", 0); clk[ckih] = imx_clk_fixed("ckih", fref); clk[ckil] = imx_clk_fixed("ckil", 32768); clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3); clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); } else { clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); } clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3); clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));