/* * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields * * Copyright (C) 2009-2010 Texas Instruments, Inc. * * Benoit Cousson (b-cousson@ti.com) * Santosh Shilimkar (santosh.shilimkar@ti.com) * * This file is automatically generated from the OMAP hardware databases. * We respectfully ask that any modifications to this file be coordinated * with the public linux-omap@vger.kernel.org mailing list and the * authors above to ensure that the autogeneration scripts are kept * up-to-date with the file contents. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H /* Base address */ #define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 /* Registers offset */ #define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 #define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 #define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c /* Registers shifts and masks */ /* IP_REVISION */ #define OMAP4_IP_REV_SCHEME_SHIFT 30 #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) #define OMAP4_IP_REV_FUNC_SHIFT 16 #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) #define OMAP4_IP_REV_RTL_SHIFT 11 #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) #define OMAP4_IP_REV_MAJOR_SHIFT 8 #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) #define OMAP4_IP_REV_CUSTOM_SHIFT 6 #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) #define OMAP4_IP_REV_MINOR_SHIFT 0 #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) /* IP_HWINFO */ #define OMAP4_IP_HWINFO_SHIFT 0 #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) /* IP_SYSCONFIG */ #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) /* PADCONF_WAKEUPEVENT_0 */ #define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 #define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) #define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 #define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) #define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 #define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) #define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 #define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) #define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 #define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) #define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 #define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) #define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 #define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) #define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 #define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) #define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 #define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) #define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 #define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) #define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 #define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) #define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 #define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) #define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 #define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) #define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 #define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) #define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 #define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) #define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 #define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) #define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 #define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) #define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 #define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) #define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 #define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) #define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 #define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) #define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 #define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) #define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 #define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) #define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 #define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) #define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 #define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) #define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 #define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) #define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 #define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) #define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 #define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) #define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 #define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) #define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 #define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) #define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 #define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) #define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 #define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) #define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 #define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) /* PADCONF_WAKEUPEVENT_1 */ #define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 #define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) #define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 #define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) #define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 #define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) #define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 #define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)