/*
 * Copyright (C) 2009 Nokia
 * Copyright (C) 2009 Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define OMAP2430_CONTROL_PADCONF_MUX_PBASE			0x49002030LU

#define OMAP2430_MUX(mode0, mux_value)					\
{									\
	.reg_offset	= (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET),	\
	.value		= (mux_value),					\
}

/*
 * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing
 *
 * Extracted from the TRM.  Add 0x49002030 to these values to get the
 * absolute addresses.  The name in the macro is the mode-0 name of
 * the pin.  NOTE: These registers are 8-bits wide.
 *
 * Note that these defines use SDMMC instead of MMC for compatibility
 * with signal names used in 3630.
 */
#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET		0x000
#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET		0x001
#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET		0x002
#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET		0x003
#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET		0x004
#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET		0x005
#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET		0x006
#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET		0x007
#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET		0x008
#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET		0x009
#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET		0x00a
#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET		0x00b
#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET		0x00c
#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET		0x00d
#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET		0x00e
#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET		0x00f
#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET		0x010
#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET		0x011
#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET		0x012
#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET		0x013
#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET		0x014
#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET		0x015
#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET		0x016
#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET		0x017
#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET		0x018
#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET		0x019
#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET		0x01a
#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET		0x01b
#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET		0x01c
#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET		0x01d
#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET		0x01e
#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET		0x01f
#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET		0x020
#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET		0x021
#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET		0x022
#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET		0x023
#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET		0x024
#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET		0x025
#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET		0x026
#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET		0x027
#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET		0x028
#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET		0x029