/* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2008 by Sascha Hauer * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * MA 02110-1301, USA. */ #ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ #define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ #define CKIH_CLK_FREQ 26000000 #define CKIH_CLK_FREQ_27MHZ 27000000 #define CKIL_CLK_FREQ 32768 extern void __iomem *mx3_ccm_base; /* Register addresses */ #define MXC_CCM_CCMR 0x00 #define MXC_CCM_PDR0 0x04 #define MXC_CCM_PDR1 0x08 #define MX35_CCM_PDR2 0x0C #define MXC_CCM_RCSR 0x0C #define MX35_CCM_PDR3 0x10 #define MXC_CCM_MPCTL 0x10 #define MX35_CCM_PDR4 0x14 #define MXC_CCM_UPCTL 0x14 #define MX35_CCM_RCSR 0x18 #define MXC_CCM_SRPCTL 0x18 #define MX35_CCM_MPCTL 0x1C #define MXC_CCM_COSR 0x1C #define MX35_CCM_PPCTL 0x20 #define MXC_CCM_CGR0 0x20 #define MX35_CCM_ACMR 0x24 #define MXC_CCM_CGR1 0x24 #define MX35_CCM_COSR 0x28 #define MXC_CCM_CGR2 0x28 #define MX35_CCM_CGR0 0x2C #define MXC_CCM_WIMR 0x2C #define MX35_CCM_CGR1 0x30 #define MXC_CCM_LDC 0x30 #define MX35_CCM_CGR2 0x34 #define MXC_CCM_DCVR0 0x34 #define MX35_CCM_CGR3 0x38 #define MXC_CCM_DCVR1 0x38 #define MXC_CCM_DCVR2 0x3C #define MXC_CCM_DCVR3 0x40 #define MXC_CCM_LTR0 0x44 #define MXC_CCM_LTR1 0x48 #define MXC_CCM_LTR2 0x4C #define MXC_CCM_LTR3 0x50 #define MXC_CCM_LTBR0 0x54 #define MXC_CCM_LTBR1 0x58 #define MXC_CCM_PMCR0 0x5C #define MXC_CCM_PMCR1 0x60 #define MXC_CCM_PDR2 0x64 /* Register bit definitions */ #define MXC_CCM_CCMR_WBEN (1 << 27) #define MXC_CCM_CCMR_CSCS (1 << 25) #define MXC_CCM_CCMR_PERCS (1 << 24) #define MXC_CCM_CCMR_SSI1S_OFFSET 18 #define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) #define MXC_CCM_CCMR_SSI2S_OFFSET 21 #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) #define MXC_CCM_CCMR_LPM_OFFSET 14 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) #define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14) #define MXC_CCM_CCMR_FIRS_OFFSET 11 #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) #define MXC_CCM_CCMR_UPE (1 << 9) #define MXC_CCM_CCMR_SPE (1 << 8) #define MXC_CCM_CCMR_MDS (1 << 7) #define MXC_CCM_CCMR_SBYCS (1 << 4) #define MXC_CCM_CCMR_MPE (1 << 3) #define MXC_CCM_CCMR_PRCS_OFFSET 1 #define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1)