/* * Copyright(c) 2006, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. * */ #ifndef _ADMA_H #define _ADMA_H #include #include #include #include #define ADMA_ACCR(chan) (chan->mmr_base + 0x0) #define ADMA_ACSR(chan) (chan->mmr_base + 0x4) #define ADMA_ADAR(chan) (chan->mmr_base + 0x8) #define ADMA_IIPCR(chan) (chan->mmr_base + 0x18) #define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) #define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) #define ADMA_ANDAR(chan) (chan->mmr_base + 0x24) #define ADMA_ADCR(chan) (chan->mmr_base + 0x28) #define ADMA_CARMD(chan) (chan->mmr_base + 0x2c) #define ADMA_ABCR(chan) (chan->mmr_base + 0x30) #define ADMA_DLADR(chan) (chan->mmr_base + 0x34) #define ADMA_DUADR(chan) (chan->mmr_base + 0x38) #define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3))) #define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3))) struct iop13xx_adma_src { u32 src_addr; union { u32 upper_src_addr; struct { unsigned int pq_upper_src_addr:24; unsigned int pq_dmlt:8; }; }; }; struct iop13xx_adma_desc_ctrl { unsigned int int_en:1; unsigned int xfer_dir:2; unsigned int src_select:4; unsigned int zero_result:1; unsigned int block_fill_en:1; unsigned int crc_gen_en:1; unsigned int crc_xfer_dis:1; unsigned int crc_seed_fetch_dis:1; unsigned int status_write_back_en:1; unsigned int endian_swap_en:1; unsigned int reserved0:2; unsigned int pq_update_xfer_en:1; unsigned int dual_xor_en:1; unsigned int pq_xfer_en:1; unsigned int p_xfer_dis:1; unsigned int reserved1:10; unsigned int relax_order_en:1; unsigned int no_snoop_en:1; }; struct iop13xx_adma_byte_count { unsigned int byte_count:24; unsigned int host_if:3; unsigned int reserved:2; unsigned int zero_result_err_q:1; unsigned int zero_result_err:1; unsigned int tx_complete:1; }; struct iop13xx_adma_desc_hw { u32 next_desc; union { u32 desc_ctrl; struct iop13xx_adma_desc_ctrl desc_ctrl_field; }; union { u32 crc_addr; u32 block_fill_data; u32 q_dest_addr; }; union { u32 byte_count; struct iop13xx_adma_byte_count byte_count_field; }; union { u32 dest_addr; u32 p_dest_addr; }; union { u32 upper_dest_addr; u32 pq_upper_dest_addr; }; struct iop13xx_adma_src src[1]; }; struct iop13xx_adma_desc_dual_xor { u32 next_desc; u32 desc_ctrl; u32 reserved; u32 byte_count; u32 h_dest_addr; u32 h_upper_dest_addr; u32 src0_addr; u32 upper_src0_addr; u32 src1_addr; u32 upper_src1_addr; u32 h_src_addr; u32 h_upper_src_addr; u32 d_src_addr; u32 d_upper_src_addr; u32 d_dest_addr; u32 d_upper_dest_addr; }; struct iop13xx_adma_desc_pq_update { u32 next_desc; u32 desc_ctrl; u32 reserved; u32 byte_count; u32 p_dest_addr; u32 p_upper_dest_addr; u32 src0_addr; u32 upper_src0_addr; u32 src1_addr; u32 upper_src1_addr; u32 p_src_addr; u32 p_upper_src_addr; u32 q_src_addr; struct { unsigned int q_upper_src_addr:24; unsigned int q_dmlt:8; }; u32 q_dest_addr; u32 q_upper_dest_addr; }; static inline int iop_adma_get_max_xor(void) { return 16; } #define iop_adma_get_max_pq iop_adma_get_max_xor static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) { return __raw_readl(ADMA_ADAR(chan)); } static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, u32 next_desc_addr) { __raw_writel(next_desc_addr, ADMA_ANDAR(chan)); } #define ADMA_STATUS_BUSY (1 << 13) static inline char iop_chan_is_busy(struct iop_adma_chan *chan) { if (__raw_readl(ADMA_ACSR(chan)) & ADMA_STATUS_BUSY) return 1; else return 0; } static inline int iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots) { return 1; } #define iop_desc_is_aligned(x, y) 1 static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) { *slots_per_op = 1; return 1; } #define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s) static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op) { *slots_per_op = 1;