/* * SH7372 clock framework support * * Copyright (C) 2010 Magnus Damm * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include #include #include #include #include #include /* SH7372 registers */ #define FRQCRA IOMEM(0xe6150000) #define FRQCRB IOMEM(0xe6150004) #define FRQCRC IOMEM(0xe61500e0) #define FRQCRD IOMEM(0xe61500e4) #define VCLKCR1 IOMEM(0xe6150008) #define VCLKCR2 IOMEM(0xe615000c) #define VCLKCR3 IOMEM(0xe615001c) #define FMSICKCR IOMEM(0xe6150010) #define FMSOCKCR IOMEM(0xe6150014) #define FSIACKCR IOMEM(0xe6150018) #define FSIBCKCR IOMEM(0xe6150090) #define SUBCKCR IOMEM(0xe6150080) #define SPUCKCR IOMEM(0xe6150084) #define VOUCKCR IOMEM(0xe6150088) #define HDMICKCR IOMEM(0xe6150094) #define DSITCKCR IOMEM(0xe6150060) #define DSI0PCKCR IOMEM(0xe6150064) #define DSI1PCKCR IOMEM(0xe6150098) #define PLLC01CR IOMEM(0xe6150028) #define PLLC2CR IOMEM(0xe615002c) #define RMSTPCR0 IOMEM(0xe6150110) #define RMSTPCR1 IOMEM(0xe6150114) #define RMSTPCR2 IOMEM(0xe6150118) #define RMSTPCR3 IOMEM(0xe615011c) #define RMSTPCR4 IOMEM(0xe6150120) #define SMSTPCR0 IOMEM(0xe6150130) #define SMSTPCR1 IOMEM(0xe6150134) #define SMSTPCR2 IOMEM(0xe6150138) #define SMSTPCR3 IOMEM(0xe615013c) #define SMSTPCR4 IOMEM(0xe6150140) #define FSIDIVA 0xFE1F8000 #define FSIDIVB 0xFE1F8008 /* Platforms must set frequency on their DV_CLKI pin */ struct clk sh7372_dv_clki_clk = { }; /* Fixed 32 KHz root clock from EXTALR pin */ static struct clk r_clk = { .rate = 32768, }; /* * 26MHz default rate for the EXTAL1 root input clock. * If needed, reset this with clk_set_rate() from the platform code. */ struct clk sh7372_extal1_clk = { .rate = 26000000, }; /* * 48MHz default rate for the EXTAL2 root input clock. * If needed, reset this with clk_set_rate() from the platform code. */ struct clk sh7372_extal2_clk = { .rate = 48000000, }; /* A fixed divide-by-2 block */ static unsigned long div2_recalc(struct clk *clk) { return clk->parent->rate / 2; } static struct sh_clk_ops div2_clk_ops = { .recalc = div2_recalc, }; /* Divide dv_clki by two */ struct clk sh7372_dv_clki_div2_clk = { .ops = &div2_clk_ops, .parent = &sh7372_dv_clki_clk, }; /* Divide extal1 by two */ static struct clk extal1_div2_clk = { .ops = &div2_clk_ops, .parent = &sh7372_extal1_clk, }; /* Divide extal2 by two */ static struct clk extal2_div2_clk = { .ops = &div2_clk_ops, .parent = &sh7372_extal2_clk, }; /* Divide extal2 by four */ static struct clk extal2_div4_clk = { .ops = &div2_clk_ops, .parent = &extal2_div2_clk, }; /* PLLC0 and PLLC1 */ static unsigned long pllc01_recalc(struct clk *clk) { unsigned long mult = 1; if (__raw_readl(PLLC01CR) & (1 << 14)) mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2; return clk->parent->rate * mult; } static struct sh_clk_ops pllc01_clk_ops = { .recalc = pllc01_recalc, }; static struct clk pllc0_clk = { .ops = &pllc01_clk_ops, .flags = CLK_ENABLE_ON_INIT,