/* * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. * All rights reserved. * Authors: Carsten Langgaard * Maciej W. Rozycki * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. */ #ifndef _ASM_GT64120_H #define _ASM_GT64120_H #include #include #define MSK(n) ((1 << (n)) - 1) /* * Register offset addresses */ /* CPU Configuration. */ #define GT_CPU_OFS 0x000 #define GT_MULTI_OFS 0x120 /* CPU Address Decode. */ #define GT_SCS10LD_OFS 0x008 #define GT_SCS10HD_OFS 0x010 #define GT_SCS32LD_OFS 0x018 #define GT_SCS32HD_OFS 0x020 #define GT_CS20LD_OFS 0x028 #define GT_CS20HD_OFS 0x030 #define GT_CS3BOOTLD_OFS 0x038 #define GT_CS3BOOTHD_OFS 0x040 #define GT_PCI0IOLD_OFS 0x048 #define GT_PCI0IOHD_OFS 0x050 #define GT_PCI0M0LD_OFS 0x058 #define GT_PCI0M0HD_OFS 0x060 #define GT_ISD_OFS 0x068 #define GT_PCI0M1LD_OFS 0x080 #define GT_PCI0M1HD_OFS 0x088 #define GT_PCI1IOLD_OFS 0x090 #define GT_PCI1IOHD_OFS 0x098 #define GT_PCI1M0LD_OFS 0x0a0 #define GT_PCI1M0HD_OFS 0x0a8 #define GT_PCI1M1LD_OFS 0x0b0 #define GT_PCI1M1HD_OFS 0x0b8 #define GT_PCI1M1LD_OFS 0x0b0 #define GT_PCI1M1HD_OFS 0x0b8 #define GT_SCS10AR_OFS 0x0d0 #define GT_SCS32AR_OFS 0x0d8 #define GT_CS20R_OFS 0x0e0 #define GT_CS3BOOTR_OFS 0x0e8 #define GT_PCI0IOREMAP_OFS 0x0f0 #define GT_PCI0M0REMAP_OFS 0x0f8 #define GT_PCI0M1REMAP_OFS 0x100 #define GT_PCI1IOREMAP_OFS 0x108 #define GT_PCI1M0REMAP_OFS 0x110 #define GT_PCI1M1REMAP_OFS 0x118 /* CPU Error Report. */ #define GT_CPUERR_ADDRLO_OFS 0x070 #define GT_CPUERR_ADDRHI_OFS 0x078 #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ /* CPU Sync Barrier. */ #define GT_PCI0SYNC_OFS 0x0c0 #define GT_PCI1SYNC_OFS 0x0c8 /* SDRAM and Device Address Decode. */ #define GT_SCS0LD_OFS 0x400 #define GT_SCS0HD_OFS 0x404 #define GT_SCS1LD_OFS 0x408 #define GT_SCS1HD_OFS 0x40c #define GT_SCS2LD_OFS 0x410 #define GT_SCS2HD_OFS 0x414 #define GT_SCS3LD_OFS 0x418 #define GT_SCS3HD_OFS 0x41c #define GT_CS0LD_OFS 0x420 #define GT_CS0HD_OFS 0x424 #define GT_CS1LD_OFS 0x428 #define GT_CS1HD_OFS 0x42c #define GT_CS2LD_OFS 0x430 #define GT_CS2HD_OFS 0x434 #define GT_CS3LD_OFS 0x438 #define GT_CS3HD_OFS 0x43c #define GT_BOOTLD_OFS 0x440 #define GT_BOOTHD_OFS 0x444 #define GT_ADERR_OFS 0x470 /* SDRAM Configuration. */ #define GT_SDRAM_CFG_OFS 0x448 #define GT_SDRAM_OPMODE_OFS 0x474 #define GT_SDRAM_BM_OFS 0x478 #define GT_SDRAM_ADDRDECODE_OFS 0x47c /* SDRAM Parameters. */ #define GT_SDRAM_B0_OFS 0x44c #define GT_SDRAM_B1_OFS 0x450 #define GT_SDRAM_B2_OFS 0x454 #define GT_SDRAM_B3_OFS 0x458 /* Device Parameters. */ #define GT_DEV_B0_OFS 0x45c #define GT_DEV_B1_OFS 0x460 #define GT_DEV_B2_OFS 0x464 #define GT_DEV_B3_OFS 0x468 #define GT_DEV_BOOT_OFS 0x46c /* ECC. */ #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ #define GT_ECC_MEM 0x488 /* GT-64120A only */ #define GT_ECC_CALC 0x48c /* GT-64120A only */ #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ /* DMA Record. */ #define GT_DMA0_CNT_OFS 0x800 #define GT_DMA1_CNT_OFS 0x804 #define GT_DMA2_CNT_OFS 0x808 #define GT_DMA3_CNT_OFS 0x80c #define GT_DMA0_SA_OFS 0x810 #define GT_DMA1_SA_OFS 0x814 #define GT_DMA2_SA_OFS 0x818 #define GT_DMA3_SA_OFS 0x81c #define GT_DMA0_DA_OFS 0x820 #define GT_DMA1_DA_OFS 0x824 #define GT_DMA2_DA_OFS 0x828 #define GT_DMA3_DA_OFS 0x82c #define GT_DMA0_NEXT_OFS 0x830 #define GT_DMA1_NEXT_OFS 0x834 #define GT_DMA2_NEXT_OFS 0x838