/* * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF54X_H #define _DEF_BF54X_H /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ /* ************************************************************** */ /* PLL Registers */ #define PLL_CTL 0xffc00000 /* PLL Control Register */ #define PLL_DIV 0xffc00004 /* PLL Divisor Register */ #define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */ #define PLL_STAT 0xffc0000c /* PLL Status Register */ #define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */ /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ #define CHIPID 0xffc00014 /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 #define CHIPID_MANUFACTURE 0x00000FFE /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ #define SWRST 0xffc00100 /* Software Reset Register */ #define SYSCR 0xffc00104 /* System Configuration register */ /* SIC Registers */ #define SIC_RVECT 0xffc00108 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */ #define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */ #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */ #define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */ #define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */ #define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */ #define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */ #define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */ #define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */ #define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */ #define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */ #define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */ #define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */ #define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */ #define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */ #define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */ #define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */ /* Watchdog Timer Registers */ #define WDOG_CTL 0xffc00200 /* Watchdog Control Register */ #define WDOG_CNT 0xffc00204 /* Watchdog Count Register */ #define WDOG_STAT 0xffc00208 /* Watchdog Status Register */ /* RTC Registers */ #define RTC_STAT 0xffc00300 /* RTC Status Register */ #define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */ #define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */ #define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */ #define RTC_ALARM 0xffc00310 /* RTC Alarm Register */ #define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */ /* UART0 Registers */ #define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */ #define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */ #define UART0_GCTL 0xffc00408 /* Global Control Register */ #define UART0_LCR 0xffc0040c /* Line Control Register */ #define UART0_MCR 0xffc00410 /* Modem Control Register */ #define UART0_LSR 0xffc00414 /* Line Status Register */ #define UART0_MSR 0xffc00418 /* Modem Status Register */ #define UART0_SCR 0xffc0041c /* Scratch Register */ #define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */ #define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */ #define UART0_THR 0xffc00428 /* Transmit Hold Register */ #define UART0_RBR 0xffc0042c /* Receive Buffer Register */ /* SPI0 Registers */ #define SPI0_REGBASE 0xffc00500 #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ #define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */ #define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */ #define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */ #define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */ /* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ /* Two Wire Interface Registers (TWI0) */ #define TWI0_REGBASE 0xffc00700 #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ #define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */ #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ #define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */ #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ #define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */ #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ #define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */ #define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */ /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ /* SPORT1 Registers */ #define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */ #define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */ #define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */ #define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */ #define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */ #define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */ #define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */ #define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */ #define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */ #define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */ #define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */ #define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */ #define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */ #define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */ #define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */ #define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */ #define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */ #define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */ #define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */ #define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */ #define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */ #define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */ /* Asynchronous Memory Control Registers */ #define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */ #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */ #define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */ #define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */ #define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */ #define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */ #define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */ /* DDR Memory Control Registers */ #define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */ #define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */ #define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */ #define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */ #define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */ #define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */ #define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */ #define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */ /* DDR BankRead and Write Count Registers */ #define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */ #define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */ #define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */ #define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */ #define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */ #define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */ #define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */