/* * arch/arm/mach-lpc32xx/include/mach/platform.h * * Author: Kevin Wells * * Copyright (C) 2010 NXP Semiconductors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef __ASM_ARCH_PLATFORM_H #define __ASM_ARCH_PLATFORM_H #define _SBF(f, v) ((v) << (f)) #define _BIT(n) _SBF(n, 1) /* * AHB 0 physical base addresses */ #define LPC32XX_SLC_BASE 0x20020000 #define LPC32XX_SSP0_BASE 0x20084000 #define LPC32XX_SPI1_BASE 0x20088000 #define LPC32XX_SSP1_BASE 0x2008C000 #define LPC32XX_SPI2_BASE 0x20090000 #define LPC32XX_I2S0_BASE 0x20094000 #define LPC32XX_SD_BASE 0x20098000 #define LPC32XX_I2S1_BASE 0x2009C000 #define LPC32XX_MLC_BASE 0x200A8000 #define LPC32XX_AHB0_START LPC32XX_SLC_BASE #define LPC32XX_AHB0_SIZE 0x00089000 /* * AHB 1 physical base addresses */ #define LPC32XX_DMA_BASE 0x31000000 #define LPC32XX_USB_BASE 0x31020000 #define LPC32XX_USBH_BASE 0x31020000 #define LPC32XX_USB_OTG_BASE 0x31020000 #define LPC32XX_OTG_I2C_BASE 0x31020300 #define LPC32XX_LCD_BASE 0x31040000 #define LPC32XX_ETHERNET_BASE 0x31060000 #define LPC32XX_EMC_BASE 0x31080000 #define LPC32XX_ETB_CFG_BASE 0x310C0000 #define LPC32XX_ETB_DATA_BASE 0x310E0000 #define LPC32XX_AHB1_START LPC32XX_DMA_BASE #define LPC32XX_AHB1_SIZE 0x000E1000 /* * FAB physical base addresses */ #define LPC32XX_CLK_PM_BASE 0x40004000 #define LPC32XX_MIC_BASE 0x40008000 #define LPC32XX_SIC1_BASE 0x4000C000 #define LPC32XX_SIC2_BASE 0x40010000 #define LPC32XX_HS_UART1_BASE 0x40014000 #define LPC32XX_HS_UART2_BASE 0x40018000 #define LPC32XX_HS_UART7_BASE 0x4001C000 #define LPC32XX_RTC_BASE 0x40024000 #define LPC32XX_RTC_RAM_BASE 0x40024080 #define LPC32XX_GPIO_BASE 0x40028000 #define LPC32XX_PWM3_BASE 0x4002C000 #define LPC32XX_PWM4_BASE 0x40030000 #define LPC32XX_MSTIM_BASE 0x40034000 #define LPC32XX_HSTIM_BASE 0x40038000 #define LPC32XX_WDTIM_BASE 0x4003C000 #define LPC32XX_DEBUG_CTRL_BASE 0x40040000 #define LPC32XX_TIMER0_BASE 0x40044000 #define LPC32XX_ADC_BASE 0x40048000 #define LPC32XX_TIMER1_BASE 0x4004C000 #define LPC32XX_KSCAN_BASE 0x40050000 #define LPC32XX_UART_CTRL_BASE 0x40054000 #define LPC32XX_TIMER2_BASE 0x40058000 #define LPC32XX_PWM1_BASE 0x4005C000 #define LPC32XX_PWM2_BASE 0x4005C004 #define LPC32XX_TIMER3_BASE 0x40060000 /* * APB physical base addresses */ #define LPC32XX_UART3_BASE 0x40080000 #define LPC32XX_UART4_BASE 0x40088000 #define LPC32XX_UART5_BASE 0x40090000 #define LPC32XX_UART6_BASE 0x40098000 #define LPC32XX_I2C1_BASE 0x400A0000 #define LPC32XX_I2C2_BASE 0x400A8000 /* * FAB and APB base and sizing */ #define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE #define LPC32XX_FABAPB_SIZE 0x000A5000 /* * Internal memory bases and sizes */ #define LPC32XX_IRAM_BASE 0x08000000 #define LPC32XX_IROM_BASE 0x0C000000 /* * External Static Memory Bank Address Space Bases */ #define LPC32XX_EMC_CS0_BASE 0xE0000000 #define LPC32XX_EMC_CS1_BASE 0xE1000000 #define LPC32XX_EMC_CS2_BASE 0xE2000000 #define LPC32XX_EMC_CS3_BASE 0xE3000000 /* * External SDRAM Memory Bank Address Space Bases */ #define LPC32XX_EMC_DYCS0_BASE 0x80000000 #define LPC32XX_EMC_DYCS1_BASE 0xA0000000 /* * Clock and crystal information */ #define LPC32XX_MAIN_OSC_FREQ 13000000 #define LPC32XX_CLOCK_OSC_FREQ 32768 /* * Clock and Power control register offsets */ #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ (x)) #define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000) #define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014) #define LPC32XX_CLKPWR_P01_ER _PMREG(0x018) #define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C) #define LPC32XX_CLKPWR_INT_ER _PMREG(0x020) #define LPC32XX_CLKPWR_INT_RS _PMREG(0x024) #define LPC32XX_CLKPWR_INT_SR _PMREG(0x028) #define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C) #define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030) #define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034) #define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038) #define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C) #define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040) #define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044) #define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048) #define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C) #define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050) #define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054) #define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058) #define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060) #define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064) #define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068) #define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C) #define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070) #define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074) #define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078) #define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C) #define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080) #define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090) #define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4) #define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8) #define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC) #define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0) #define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4) #define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8) #define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC) #define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0) #define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4) #define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8) #define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0) #define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4) #define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8) #define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC) #define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0) #define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4) #define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8) #define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC) #define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x)) /* * clkpwr_debug_ctrl register definitions */ #define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4) /* * clkpwr_bootmap register definitions */ #define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1) /* * clkpwr_start_gpio register bit definitions */ #define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31) #define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30) #define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29) #define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28) #define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27) #define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26) #define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25) #define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24) #define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23) #define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22) #define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21) #define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20) #define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19) #define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18) #define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17) #define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16) #define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15) #define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14) #define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13) #define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12) #define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11) #define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10) #define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9) #define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8) #define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7) #define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6) #define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5) #define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4) #define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3) #define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2) #define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1) #define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0) /* * clkpwr_usbclk_pdiv register definitions */ #define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF /* * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int, * clkpwr_start_pol_int, register bit definitions */ #define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31) #define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30) #define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29) #define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26) #define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25) #define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24) #define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23) #define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22) #define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21) #define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20) #define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19) #define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16) #define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7) #define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6) #define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5) #define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4) #define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3) #define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2) #define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1) #define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0) /* * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin, * clkpwr_start_pol_pin register bit definitions */ #define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31) #define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30) #define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28) #define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26) #define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25) #define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24) #define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23) #define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22) #define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21) #define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18) #define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17) #define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16) #define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15) #define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14) #define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13) #define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12) #define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11)