/* linux/arch/arm/plat-samsung/devs.c * * Copyright (c) 2011 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Base SAMSUNG platform device definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); /* AC97 */ #ifdef CONFIG_CPU_S3C2440 static struct resource s3c_ac97_resource[] = { [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97), [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97), [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"), [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"), [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"), }; struct platform_device s3c_device_ac97 = { .name = "samsung-ac97", .id = -1, .num_resources = ARRAY_SIZE(s3c_ac97_resource), .resource = s3c_ac97_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; #endif /* CONFIG_CPU_S3C2440 */ /* ADC */ #ifdef CONFIG_PLAT_S3C24XX static struct resource s3c_adc_resource[] = { [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC), [1] = DEFINE_RES_IRQ(IRQ_TC), [2] = DEFINE_RES_IRQ(IRQ_ADC), }; struct platform_device s3c_device_adc = { .name = "s3c24xx-adc", .id = -1, .num_resources = ARRAY_SIZE(s3c_adc_resource), .resource = s3c_adc_resource, }; #endif /* CONFIG_PLAT_S3C24XX */ #if defined(CONFIG_SAMSUNG_DEV_ADC) static struct resource s3c_adc_resource[] = { [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256), [1] = DEFINE_RES_IRQ(IRQ_TC), [2] = DEFINE_RES_IRQ(IRQ_ADC), }; struct platform_device s3c_device_adc = { .name = "samsung-adc", .id = -1, .num_resources = ARRAY_SIZE(s3c_adc_resource), .resource = s3c_adc_resource, }; #endif /* CONFIG_SAMSUNG_DEV_ADC */ /* Camif Controller */ #ifdef CONFIG_CPU_S3C2440 static struct resource s3c_camif_resource[] = { [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF), [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C), [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P), }; struct platform_device s3c_device_camif = { .name = "s3c2440-camif", .id = -1, .num_resources = ARRAY_SIZE(s3c_camif_resource), .resource = s3c_camif_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; #endif /* CONFIG_CPU_S3C2440 */ /* ASOC DMA */ struct platform_device samsung_asoc_idma = { .name = "samsung-idma", .id = -1, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; /* FB */ #ifdef CONFIG_S3C_DEV_FB static struct resource s3c_fb_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K), [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC), [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO), [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM), }; struct platform_device s3c_device_fb = { .name = "s3c-fb", .id = -1, .num_resources = ARRAY_SIZE(s3c_fb_resource), .resource = s3c_fb_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) { s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), &s3c_device_fb); } #endif /* CONFIG_S3C_DEV_FB */ /* FIMC */ #ifdef CONFIG_S5P_DEV_FIMC0 static struct resource s5p_fimc0_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_FIMC0), }; struct platform_device s5p_device_fimc0 = { .name = "s5p-fimc", .id = 0, .num_resources = ARRAY_SIZE(s5p_fimc0_resource), .resource = s5p_fimc0_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; struct platform_device s5p_device_fimc_md = { .name = "s5p-fimc-md", .id = -1, }; #endif /* CONFIG_S5P_DEV_FIMC0 */ #ifdef CONFIG_S5P_DEV_FIMC1 static struct resource s5p_fimc1_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_FIMC1), }; struct platform_device s5p_device_fimc1 = { .name = "s5p-fimc", .id = 1, .num_resources = ARRAY_SIZE(s5p_fimc1_resource), .resource = s5p_fimc1_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_FIMC1 */ #ifdef CONFIG_S5P_DEV_FIMC2 static struct resource s5p_fimc2_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_FIMC2), }; struct platform_device s5p_device_fimc2 = { .name = "s5p-fimc", .id = 2, .num_resources = ARRAY_SIZE(s5p_fimc2_resource), .resource = s5p_fimc2_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_FIMC2 */ #ifdef CONFIG_S5P_DEV_FIMC3 static struct resource s5p_fimc3_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_FIMC3), }; struct platform_device s5p_device_fimc3 = { .name = "s5p-fimc", .id = 3, .num_resources = ARRAY_SIZE(s5p_fimc3_resource), .resource = s5p_fimc3_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_FIMC3 */ /* G2D */ #ifdef CONFIG_S5P_DEV_G2D static struct resource s5p_g2d_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_2D), }; struct platform_device s5p_device_g2d = { .name = "s5p-g2d", .id = 0, .num_resources = ARRAY_SIZE(s5p_g2d_resource), .resource = s5p_g2d_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_G2D */ #ifdef CONFIG_S5P_DEV_JPEG static struct resource s5p_jpeg_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_JPEG), }; struct platform_device s5p_device_jpeg = { .name = "s5p-jpeg", .id = 0, .num_resources = ARRAY_SIZE(s5p_jpeg_resource), .resource = s5p_jpeg_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #endif /* CONFIG_S5P_DEV_JPEG */ /* FIMD0 */ #ifdef CONFIG_S5P_DEV_FIMD0 static struct resource s5p_fimd0_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K), [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC), [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO), [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM), }; struct platform_device s5p_device_fimd0 = { .name = "s5p-fb", .id = 0, .num_resources = ARRAY_SIZE(s5p_fimd0_resource), .resource = s5p_fimd0_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd) { s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), &s5p_device_fimd0); } #endif /* CONFIG_S5P_DEV_FIMD0 */ /* HWMON */ #ifdef CONFIG_S3C_DEV_HWMON struct platform_device s3c_device_hwmon = { .name = "s3c-hwmon", .id = -1, .dev.parent = &s3c_device_adc.dev, }; void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd) { s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata), &s3c_device_hwmon); } #endif /* CONFIG_S3C_DEV_HWMON */ /* HSMMC */ #ifdef CONFIG_S3C_DEV_HSMMC static struct resource s3c_hsmmc_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_HSMMC0), }; struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), }; struct platform_device s3c_device_hsmmc0 = { .name = "s3c-sdhci", .id = 0, .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), .resource = s3c_hsmmc_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &s3c_hsmmc0_def_platdata, }, }; void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) { s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata); } #endif /* CONFIG_S3C_DEV_HSMMC */ #ifdef CONFIG_S3C_DEV_HSMMC1 static struct resource s3c_hsmmc1_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_HSMMC1), }; struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), }; struct platform_device s3c_device_hsmmc1 = { .name = "s3c-sdhci", .id = 1, .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource), .resource = s3c_hsmmc1_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &s3c_hsmmc1_def_platdata, }, }; void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) { s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata); } #endif /* CONFIG_S3C_DEV_HSMMC1 */ /* HSMMC2 */ #ifdef CONFIG_S3C_DEV_HSMMC2 static struct resource s3c_hsmmc2_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_HSMMC2), }; struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), }; struct platform_device s3c_device_hsmmc2 = { .name = "s3c-sdhci", .id = 2, .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource), .resource = s3c_hsmmc2_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &s3c_hsmmc2_def_platdata, }, }; void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) { s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata); } #endif /* CONFIG_S3C_DEV_HSMMC2 */ #ifdef CONFIG_S3C_DEV_HSMMC3 static struct resource s3c_hsmmc3_resource[] = { [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K), [1] = DEFINE_RES_IRQ(IRQ_HSMMC3), }; struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), }; struct platform_device s3c_device_hsmmc3 = { .name = "s3c-sdhci", .id = 3,