/* * Copyright 2005-2010 Analog Devices Inc. * * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF534_H #define _DEF_BF534_H /************************************************************************************ ** System MMR Register Map *************************************************************************************/ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define PLL_CTL 0xFFC00000 /* PLL Control Register */ #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ #define PLL_STAT 0xFFC0000C /* PLL Status Register */ #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ #define CHIPID 0xFFC00014 /* Chip ID Register */ /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration Register */ #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ #define RTC_STAT 0xFFC00300 /* RTC Status Register */ #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ #define UART0_THR 0xFFC00400 /* Transmit Holding register */ #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ #define UART0_LCR 0xFFC0040C /* Line Control Register */ #define UART0_MCR 0xFFC00410 /* Modem Control Register */ #define UART0_LSR 0xFFC00414 /* Line Status Register */ #define UART0_MSR 0xFFC00418 /* Modem Status Register */ #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ #define UART0_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ #define SPI0_REGBASE 0xFFC00500 #define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */ #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */