/* * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #ifndef _CDEF_BF54X_H #define _CDEF_BF54X_H /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ /* ************************************************************** */ /* PLL Registers */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) /* SIC Registers */ #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2)) #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val) #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2)) #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val) #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) #define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) #define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) #define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) #define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) #define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) /* Watchdog Timer Registers */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) /* RTC Registers */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) /* UART0 Registers */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) #define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) #define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) /* SPI0 Registers */ #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) /* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ /* Two Wire Interface Registers (TWI0) */ /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)