/* * FILE SA-1100.h * * Version 1.2 * Author Copyright (c) Marc A. Viredaz, 1998 * DEC Western Research Laboratory, Palo Alto, CA * Date January 1998 (April 1997) * System StrongARM SA-1100 * Language C or ARM Assembly * Purpose Definition of constants related to the StrongARM * SA-1100 microprocessor (Advanced RISC Machine (ARM) * architecture version 4). This file is based on the * StrongARM SA-1100 data sheet version 2.2. * */ /* Be sure that virtual mapping is defined right */ #ifndef __ASM_ARCH_HARDWARE_H #error You must include hardware.h not SA-1100.h #endif #include "bitfield.h" /* * SA1100 CS line to physical address */ #define SA1100_CS0_PHYS 0x00000000 #define SA1100_CS1_PHYS 0x08000000 #define SA1100_CS2_PHYS 0x10000000 #define SA1100_CS3_PHYS 0x18000000 #define SA1100_CS4_PHYS 0x40000000 #define SA1100_CS5_PHYS 0x48000000 /* * Personal Computer Memory Card International Association (PCMCIA) sockets */ #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ (0x20000000 + (Nb)*PCMCIASp) #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ (_PCMCIA (Nb) + 2*PCMCIAPrtSp) #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ (_PCMCIA (Nb) + 3*PCMCIAPrtSp) #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ /* * Universal Serial Bus (USB) Device Controller (UDC) control registers * * Registers * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control Register (read/write). * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Address Register (read/write). * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Output Maximum Packet size register * (read/write). * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Input Maximum Packet size register * (read/write). * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 0 * (read/write). * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 1 * (output, read/write). * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 2 * (input, read/write). * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Data register end-point 0 * (read/write). * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Write Count register end-point 0 * (read). * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Data Register (read/write). * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Status Register (read/write). */ #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ #define UDCCR_UDD 0x00000001 /* UDC Disable */ #define UDCCR_UDA 0x00000002 /* UDC Active (read) */ #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ /* (disable) */ #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ /* (disable) */ #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ /* (disable) */ #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ /* (disable) */ #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ #define UDCAR_ADD Fld (7, 0) /* function ADDress */ #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ /* [byte] */ #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ /* [byte] */ #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCIMP_INMAXP)) #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ #define UDCCS0_SST 0x00000004 /* Sent STall */ #define UDCCS0_FST 0x00000008 /* Force STall */ #define UDCCS0_DE 0x00000010 /* Data End */ #define UDCCS0_SE 0x00000020 /* Setup End (read) */ #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ /* (write) */ #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ /* Service request (read) */ #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ #define UDCCS1_SST 0x00000008 /* Sent STall */ #define UDCCS1_FST 0x00000010 /* Force STall */ #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ /* Service request (read) */ #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ #define UDCCS2_SST 0x00000010 /* Sent STall */ #define UDCCS2_FST 0x00000020 /* Force STall */ #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #define UDCWC_WC Fld (4, 0) /* Write Count */ #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ /* * Universal Asynchronous Receiver/Transmitter (UART) control registers * * Registers * Ser1UTCR0 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 0 * (read/write). * Ser1UTCR1 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 1 * (read/write). * Ser1UTCR2 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 2 * (read/write). * Ser1UTCR3 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 3 * (read/write). * Ser1UTDR Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Data Register * (read/write). * Ser1UTSR0 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 0 * (read/write). * Ser1UTSR1 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 1 (read). * * Ser2UTCR0 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 0 * (read/write). * Ser2UTCR1 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 1 * (read/write). * Ser2UTCR2 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 2 * (read/write). * Ser2UTCR3 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 3 * (read/write). * Ser2UTCR4 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 4 * (read/write). * Ser2UTDR Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Data Register * (read/write). * Ser2UTSR0 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 0 * (read/write). * Ser2UTSR1 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 1 (read). * * Ser3UTCR0 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 0 * (read/write). * Ser3UTCR1 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 1 * (read/write). * Ser3UTCR2 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 2 * (read/write). * Ser3UTCR3 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 3 * (read/write). * Ser3UTDR Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Data Register * (read/write). * Ser3UTSR0 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 0 * (read/write). * Ser3UTSR1 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 1 (read). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz * or 3.5795 MHz). * fua, Tua Frequency, period of the UART communication. */ #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ #define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ #define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ #define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ #define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ #define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ #define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ #define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ /* Those are still used in some places */ #define _Ser1UTCR0 __PREG(Ser1UTCR0) #define _Ser2UTCR0 __PREG(Ser2UTCR0) #define _Ser3UTCR0 __PREG(Ser3UTCR0) /* Register offsets */ #define UTCR0 0x00 #define UTCR1 0x04 #define UTCR2 0x08 #define UTCR3 0x0c #define UTDR 0x14 #define UTSR0 0x1c #define UTSR1 0x20 #define UTCR0_PE 0x00000001 /* Parity Enable */ #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ #define UTCR0_SBS 0x00000004 /* Stop Bit Select */ #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ #define UTCR0_DSS 0x00000008 /* Data Size Select */ #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ /* (ser. port 1: GPIO [18], */ /* ser. port 3: GPIO [20]) */ #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ (UTCR0_1StpBit + UTCR0_8BitData) #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ /* fua = fxtl/(16*(BRD[11:0] + 1)) */ /* Tua = 16*(BRD [11:0] + 1)*Txtl */ #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ FShft (UTCR1_BRD)) #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ FShft (UTCR2_BRD)) /* fua = fxtl/(16*Floor (Div/16)) */ /* Tua = 16*Floor (Div/16)*Txtl */ #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ FShft (UTCR1_BRD)) #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ FShft (UTCR2_BRD)) /* fua = fxtl/(16*Ceil (Div/16)) */ /* Tua = 16*Ceil (Div/16)*Txtl */ #define UTCR3_RXE 0x00000001 /* Receive Enable */ #define UTCR3_TXE 0x00000002 /* Transmit Enable */ #define UTCR3_BRK 0x00000004 /* BReaK mode */ #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ /* more Interrupt Enable */ #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ /* Interrupt Enable */ #define UTCR3_LBM 0x00000020 /* Look-Back Mode */ #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ /* TIE, LBM can be set or cleared) */ \ (UTCR3_RXE + UTCR3_TXE) #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ /* (HP-SIR) modulation Enable */ #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ #define UTCR4_LPM 0x00000002 /* Low-Power Mode */ #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #if 0 /* Hidden receive FIFO bits */ #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ /* Service request (read) */ #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ /* more Service request (read) */ #define UTSR0_RID 0x00000004 /* Receiver IDle */ #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ #define UTSR0_REB 0x00000010 /* Receive End of Break */ #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ /* * Synchronous Data Link Controller (SDLC) control registers * * Registers * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 0 (read/write). * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 1 (read/write). * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 2 (read/write). * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 3 (read/write). * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 4 (read/write). * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) * Data Register (read/write). * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) * Status Register 0 (read/write). * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) * Status Register 1 (read/write). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz * or 3.5795 MHz). * fsd, Tsd Frequency, period of the SDLC communication. */ #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */ #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */ #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */ #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */ #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */ #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */ #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */ #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ #define SDCR0_LBM 0x00000004 /* Look-Back Mode */ #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */