/* * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF538_H #define _DEF_BF538_H /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */ #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ #define CHIPID 0xFFC00014 /* Chip ID Register */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 #define CHIPID_MANUFACTURE 0x00000FFE /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ #define SYSCR 0xFFC00104 /* System Configuration registe */ #define SIC_RVECT 0xFFC00108 #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ #define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ #define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ #define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ #define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ #define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ #define RTC_STAT 0xFFC00300 /* RTC Status Register */ #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ #define UART0_THR 0xFFC00400 /* Transmit Holding register */ #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ #define UART0_LCR 0xFFC0040C /* Line Control Register */ #define UART0_MCR 0xFFC00410 /* Modem Control Register */ #define UART0_LSR 0xFFC00414 /* Line Status Register */ #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ #define UART0_GCTL 0xFFC00424 /* Global Control Register */ /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ #define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ #define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ #define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ #define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ #define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ #define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ #define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ #define SPI0_REGBASE SPI0_CTL /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ /* Programmable Flags (0xFFC00700 - 0xFFC007FF) */ #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ /* Asynchronous Memory Controller */ #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ /* SDRAM Controller */ #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ /* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ #define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ #define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */ /* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */ #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */ #define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */ #define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */ #define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */ #define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */ #define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */ #define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */ #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */ #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */ #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */ #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */ #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */ #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */ #define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */ #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */ #define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */ #define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */ #define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */ #define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */ #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */ #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */ #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */ #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */ #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */ #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */ #define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */ #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */ #define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */ #define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */ #define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */ #define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */ #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */ #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */ #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */ #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */ #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */ #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */ #define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */ #define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */ #define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */ #define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */ #define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */ #define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */ #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */ #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */ #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */ #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ #define TWI0_REGBASE TWI0_CLKDIV /* the following are for backwards compatibility */ #define TWI0_PRESCALE TWI0_CONTROL #define TWI0_INT_SRC TWI0_INT_STAT #define TWI0_INT_ENABLE TWI0_INT_MASK /* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ /* GPIO Port C Register Names */ #define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ #define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ #define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ #define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ #define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ #define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ #define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ /* GPIO Port D Register Names */ #define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ #define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ #define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ #define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ #define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ #define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ #define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ /* GPIO Port E Register Names */ #define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ #define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ #define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ #define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ #define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ #define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ #define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ #define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ #define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */ /* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */ #define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */ #define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */ #define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */ #define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */ #define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */ #define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */ #define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */ #define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ #define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ #define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ #define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */ #define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ #define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ #define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */ #define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */ #define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */ #define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */ #define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */ #define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */ #define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */ #define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ #define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ #define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */ #define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */ #define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ #define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ #define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */ #define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */ #define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */ #define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */ #define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */ #define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */ #define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */ #define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ #define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ #define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ #define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */ #define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ #define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ #define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */ #define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */ #define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */ #define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */ #define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */ #define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */ #define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */ #define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ #define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ #define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */ #define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */ #define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ #define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ #define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */ #define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */ #define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */ #define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */ #define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */ #define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */ #define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */ #define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ #define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ #define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ #define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */ #define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ #define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ #define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */ #define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */ #define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */ #define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */ #define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */ #define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */ #define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */ #define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ #define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ #define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */ #define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */ #define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ #define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ #define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */ #define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */ #define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */ #define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */ #define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */ #define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */ #define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */ #define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ #define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ #define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ #define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */ #define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ #define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ #define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */ #define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */ #define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */ #define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */ #define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */ #define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */ #define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */ #define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ #define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ #define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ #define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */ #define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ #define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ #define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */ #define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */ #define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */ #define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */ #define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */ #define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */ #define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */ #define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ #define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ #define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */ #define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */ #define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ #define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ #define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */ #define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */ #define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */ #define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */ #define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */ #define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */ #define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */ #define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ #define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ #define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ #define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */ #define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ #define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ #define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */ #define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */ #define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */ #define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */ #define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */ #define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */ #define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */ #define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ #define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ #define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */ #define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */ #define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ #define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ #define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */ #define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */ #define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */ #define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */ #define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */ #define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */ #define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */ #define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ #define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ #define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */ #define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */ #define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ #define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ #define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */ #define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */ #define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */ #define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */ #define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */ #define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */ #define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */ #define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ #define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ #define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ #define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */ #define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ #define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ #define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */ #define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */ #define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */ #define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */ #define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */ #define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */ #define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */ #define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ #define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ #define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */ #define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */ #define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ #define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ #define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */ #define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */ #define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */ #define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */ #define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */ #define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */ #define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */ #define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ #define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ #define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */ #define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */ #define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ #define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ #define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */ #define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */ #define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */ #define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */ #define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */ #define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */ #define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */ #define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ #define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ #define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */ #define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */ #define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ #define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ #define UART1_THR 0xFFC02000 /* Transmit Holding register */ #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ #define UART1_LCR 0xFFC0200C /* Line Control Register */ #define UART1_MCR 0xFFC02010 /* Modem Control Register */ #define UART1_LSR 0xFFC02014 /* Line Status Register */ #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ #define UART1_GCTL 0xFFC02024 /* Global Control Register */ /* UART2 Controller (0xFFC02100 - 0xFFC021FF) */ #define UART2_THR 0xFFC02100 /* Transmit Holding register */ #define UART2_RBR 0xFFC02100 /* Receive Buffer register */ #define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */ #define UART2_IER 0xFFC02104 /* Interrupt Enable Register */ #define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */ #define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */ #define UART2_LCR 0xFFC0210C /* Line Control Register */ #define UART2_MCR 0xFFC02110 /* Modem Control Register */ #define UART2_LSR 0xFFC02114 /* Line Status Register */ #define UART2_SCR 0xFFC0211C /* SCR Scratch Register */ #define UART2_GCTL 0xFFC02124 /* Global Control Register */ /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ #define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ #define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ #define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ #define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ #define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ #define TWI1_REGBASE TWI1_CLKDIV /* the following are for backwards compatibility */ #define TWI1_PRESCALE TWI1_CONTROL #define TWI1_INT_SRC TWI1_INT_STAT #define TWI1_INT_ENABLE TWI1_INT_MASK /* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */ #define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ #define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */ #define SPI1_STAT 0xFFC02308 /* SPI1 Status register */ #define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ #define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ #define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */ #define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */ #define SPI1_REGBASE SPI1_CTL /* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */ #define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ #define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */ #define SPI2_STAT 0xFFC02408 /* SPI2 Status register */ #define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ #define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ #define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */ #define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */ #define SPI2_REGBASE SPI2_CTL /* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */ #define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ #define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ #define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */ #define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */ #define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */ #define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */ #define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */ #define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */ #define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ #define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */ #define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ #define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ #define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */ #define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */ #define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */ #define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */ #define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */ #define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */ #define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ #define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */ #define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */ #define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */ /* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */ #define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ #define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ #define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */ #define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */ #define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */ #define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */ #define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */ #define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */ #define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ #define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */ #define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ #define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ #define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */ #define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */ #define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */ #define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */ #define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */ #define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */ #define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ #define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */