/* include/asm-m68knommu/MC68328.h: '328 control registers * * Copyright (C) 1999 Vladimir Gurevich * Bear & Hare Software, Inc. * * Based on include/asm-m68knommu/MC68332.h * Copyright (C) 1998 Kenneth Albanowski , * */ #ifndef _MC68328_H_ #define _MC68328_H_ #define BYTE_REF(addr) (*((volatile unsigned char*)addr)) #define WORD_REF(addr) (*((volatile unsigned short*)addr)) #define LONG_REF(addr) (*((volatile unsigned long*)addr)) #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) /********** * * 0xFFFFF0xx -- System Control * **********/ /* * System Control Register (SCR) */ #define SCR_ADDR 0xfffff000 #define SCR BYTE_REF(SCR_ADDR) #define SCR_WDTH8 0x01 /* 8-Bit Width Select */ #define SCR_DMAP 0x04 /* Double Map */ #define SCR_SO 0x08 /* Supervisor Only */ #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ #define SCR_PRV 0x20 /* Privilege Violation */ #define SCR_WPV 0x40 /* Write Protect Violation */ #define SCR_BETO 0x80 /* Bus-Error TimeOut */ /* * Mask Revision Register */ #define MRR_ADDR 0xfffff004 #define MRR LONG_REF(MRR_ADDR) /********** * * 0xFFFFF1xx -- Chip-Select logic * **********/ /********** * * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control * **********/ /* * Group Base Address Registers */ #define GRPBASEA_ADDR 0xfffff100 #define GRPBASEB_ADDR 0xfffff102 #define GRPBASEC_ADDR 0xfffff104 #define GRPBASED_ADDR 0xfffff106 #define GRPBASEA WORD_REF(GRPBASEA_ADDR) #define GRPBASEB WORD_REF(GRPBASEB_ADDR) #define GRPBASEC WORD_REF(GRPBASEC_ADDR) #define GRPBASED WORD_REF(GRPBASED_ADDR) #define GRPBASE_V 0x0001 /* Valid */ #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */ /* * Group Base Address Mask Registers */ #define GRPMASKA_ADDR 0xfffff108 #define GRPMASKB_ADDR 0xfffff10a #define GRPMASKC_ADDR 0xfffff10c #define GRPMASKD_ADDR 0xfffff10e #define GRPMASKA WORD_REF(GRPMASKA_ADDR) #define GRPMASKB WORD_REF(GRPMASKB_ADDR) #define GRPMASKC WORD_REF(GRPMASKC_ADDR) #define GRPMASKD WORD_REF(GRPMASKD_ADDR) #define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */ /* * Chip-Select Option Registers (group A) */ #define CSA0_ADDR 0xfffff110 #define CSA1_ADDR 0xfffff114 #define CSA2_ADDR 0xfffff118 #define CSA3_ADDR 0xfffff11c #define CSA0 LONG_REF(CSA0_ADDR) #define CSA1 LONG_REF(CSA1_ADDR) #define CSA2 LONG_REF(CSA2_ADDR) #define CSA3 LONG_REF(CSA3_ADDR) #define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */ #define CSA_WAIT_SHIFT 0 #define CSA_RO 0x00000008 /* Read-Only */ #define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ #define CSA_AM_SHIFT 8 #define CSA_BUSW 0x00010000 /* Bus Width Select */ #define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ #define CSA_AC_SHIFT 24 /* * Chip-Select Option Registers (group B) */ #define CSB0_ADDR 0xfffff120 #define CSB1_ADDR 0xfffff124 #define CSB2_ADDR 0xfffff128 #define CSB3_ADDR 0xfffff12c #define CSB0 LONG_REF(CSB0_ADDR) #define CSB1 LONG_REF(CSB1_ADDR) #define CSB2 LONG_REF(CSB2_ADDR) #define CSB3 LONG_REF(CSB3_ADDR) #define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */ #define CSB_WAIT_SHIFT 0 #define CSB_RO 0x00000008 /* Read-Only */ #define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ #define CSB_AM_SHIFT 8 #define CSB_BUSW 0x00010000 /* Bus Width Select */ #define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ #define CSB_AC_SHIFT 24 /* * Chip-Select Option Registers (group C) */ #define CSC0_ADDR 0xfffff130 #define CSC1_ADDR 0xfffff134 #define CSC2_ADDR 0xfffff138 #define CSC3_ADDR 0xfffff13c #define CSC0 LONG_REF(CSC0_ADDR) #define CSC1 LONG_REF(CSC1_ADDR) #define CSC2 LONG_REF(CSC2_ADDR) #define CSC3 LONG_REF(CSC3_ADDR) #define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */ #define CSC_WAIT_SHIFT 0 #define CSC_RO 0x00000008 /* Read-Only */ #define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ #define CSC_AM_SHIFT 4 #define CSC_BUSW 0x00010000 /* Bus Width Select */ #define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ #define CSC_AC_SHIFT 20 /* * Chip-Select Option Registers (group D) */ #define CSD0_ADDR 0xfffff140 #define CSD1_ADDR 0xfffff144 #define CSD2_ADDR 0xfffff148 #define CSD3_ADDR 0xfffff14c #define CSD0 LONG_REF(CSD0_ADDR) #define CSD1 LONG_REF(CSD1_ADDR) #define CSD2 LONG_REF(CSD2_ADDR) #define CSD3 LONG_REF(CSD3_ADDR) #define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */ #define CSD_WAIT_SHIFT 0 #define CSD_RO 0x00000008 /* Read-Only */ #define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ #define CSD_AM_SHIFT 4 #define CSD_BUSW 0x00010000 /* Bus Width Select */ #define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ #define CSD_AC_SHIFT 20 /********** * * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control * **********/ /* * PLL Control Register */ #define PLLCR_ADDR 0xfffff200 #define PLLCR WORD_REF(PLLCR_ADDR) #define PLLCR_DISPLL 0x0008 /* Disable PLL */ #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ #define PLLCR_SYSCLK_SEL_SHIFT 8 #define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ #define PLLCR_PIXCLK_SEL_SHIFT 11 /* 'EZ328-compatible definitions */ #define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK #define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT /* * PLL Frequency Select Register */ #define PLLFSR_ADDR 0xfffff202 #define PLLFSR WORD_REF(PLLFSR_ADDR) #define PLLFSR_PC_MASK 0x00ff /* P Count */ #define PLLFSR_PC_SHIFT 0 #define PLLFSR_QC_MASK 0x0f00 /* Q Count */ #define PLLFSR_QC_SHIFT 8 #define PLLFSR_PROT 0x4000 /* Protect P & Q */ #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ /* * Power Control Register */ #define PCTRL_ADDR 0xfffff207 #define PCTRL BYTE_REF(PCTRL_ADDR) #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ #define PCTRL_WIDTH_SHIFT 0 #define PCTRL_STOP 0x40 /* Enter power-save mode immediately */ #define PCTRL_PCEN 0x80 /* Power Control Enable */ /********** * * 0xFFFFF3xx -- Interrupt Controller * **********/ /* * Interrupt Vector Register */ #define IVR_ADDR 0xfffff300 #define IVR BYTE_REF(IVR_ADDR) #define IVR_VECTOR_MASK 0xF8 /* * Interrupt control Register */ #define ICR_ADRR 0xfffff302 #define ICR WORD_REF(ICR_ADDR) #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ /* * Interrupt Mask Register */ #define IMR_ADDR 0xfffff304 #define IMR LONG_REF(IMR_ADDR) /* * Define the names for bit positions first. This is useful for * request_irq */ #define SPIM_IRQ_NUM 0 /* SPI Master interrupt */ #define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */ #define UART_IRQ_NUM 2 /* UART interrupt */ #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ #define RTC_IRQ_NUM 4 /* RTC interrupt */ #define KB_IRQ_NUM 6 /* Keyboard Interrupt */ #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */ #define INT0_IRQ_NUM 8 /* External INT0 */ #define INT1_IRQ_NUM 9 /* External INT1 */ #define INT2_IRQ_NUM 10 /* External INT2 */ #define INT3_IRQ_NUM 11 /* External INT3 */ #define INT4_IRQ_NUM 12 /* External INT4 */ #define INT5_IRQ_NUM 13 /* External INT5 */ #define INT6_IRQ_NUM 14 /* External INT6 */ #define INT7_IRQ_NUM 15 /* External INT7 */ #define IRQ1_IRQ_NUM 16 /* IRQ1 */ #define IRQ2_IRQ_NUM 17 /* IRQ2 */ #define IRQ3_IRQ_NUM 18 /* IRQ3 */ #define IRQ6_IRQ_NUM 19 /* IRQ6 */ #define PEN_IRQ_NUM 20 /* Pen Interrupt */ #define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */ #define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */ #define IRQ7_IRQ_NUM 23 /* IRQ7 */ /* '328-compatible definitions */ #define SPI_IRQ_NUM SPIM_IRQ_NUM #define TMR_IRQ_NUM TMR1_IRQ_NUM /* * Here go the bitmasks themselves */ #define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */ #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */ #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ #define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */ #define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */ #define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */ #define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */ #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ #define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */ #define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */ #define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */ #define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */ /* 'EZ328-compatible definitions */ #define IMR_MSPI IMR_MSPIM #define IMR_MTMR IMR_MTMR1 /* * Interrupt Wake-Up Enable Register */ #define IWR_ADDR 0xfffff308 #define IWR LONG_REF(IWR_ADDR) #define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ #define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ #define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ #define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ #define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ #define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ #define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ #define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ #define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ #define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ #define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ #define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ #define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ #define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ #define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ #define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ #define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ #define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ #define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ #define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ #define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ #define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ /* * Interrupt Status Register */ #define ISR_ADDR 0xfffff30c #define ISR LONG_REF(ISR_ADDR) #define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ #define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ #define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ #define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ #define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ #define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */