/* * arch/arm/include/asm/io.h * * Copyright (C) 1996-2000 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Modifications: * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both * constant addresses and variable addresses. * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture * specific IO header files. * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. * 04-Apr-1999 PJB Added check_signature. * 12-Dec-1999 RMK More cleanups * 18-Jun-2000 RMK Removed virt_to_* and friends definitions * 05-Oct-2004 BJD Moved memory string functions to use void __iomem */ #ifndef __ASM_ARM_IO_H #define __ASM_ARM_IO_H #ifdef __KERNEL__ #include #include #include #include /* * ISA I/O bus memory addresses are 1:1 with the physical address. */ #define isa_virt_to_bus virt_to_phys #define isa_page_to_bus page_to_phys #define isa_bus_to_virt phys_to_virt /* * Generic IO read/write. These perform native-endian accesses. Note * that some architectures will want to re-define __raw_{read,write}w. */ extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen); extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); extern void __raw_writesl(void __iomem *addr, const void *data, int longlen); extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); #if __LINUX_ARM_ARCH__ < 6 /* * Half-word accesses are problematic with RiscPC due to limitations of * the bus. Rather than special-case the machine, just let the compiler * generate the access for CPUs prior to ARMv6. */ #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) #else /* * When running under a hypervisor, we want to avoid I/O accesses with * writeback addressing modes as these incur a significant performance * overhead (the address generation must be emulated in software). */ static inline void __raw_writew(u16 val, volatile void __iomem *addr) { asm volatile("strh %1, %0" : "+Q" (*(volatile u16 __force *)addr) : "r" (val)); } static inline u16 __raw_readw(const volatile void __iomem *addr) { u16 val; asm volatile("ldrh %1, %0" : "+Q" (*(volatile u16 __force *)addr), "=r" (val)); return val; } #endif static inline void __raw_writeb(u8 val, volatile void __iomem *addr) { asm volatile("strb %1, %0" : "+Qo" (*(volatile u8 __force *)addr) : "r" (val)); } static inline void __raw_writel(u32 val, volatile void __iomem *addr) { asm volatile("str %1, %0" : "+Qo" (*(volatile u32 __force *)addr) : "r" (val)); } static inline u8 __raw_readb(const volatile void __iomem *addr) { u8 val; asm volatile("ldrb %1, %0" : "+Qo" (*(volatile u8 __force *)addr), "=r" (val)); return val; } static inline u32 __raw_readl(const volatile void __iomem *addr) { u32 val; asm volatile("ldr %1, %0" : "+Qo" (*(volatile u32 __force *)addr), "=r" (val)); return val; } /* * Architecture ioremap implementation. */ #define MT_DEVICE 0 #define MT_DEVICE_NONSHARED 1 #define MT_DEVICE_CACHED 2 #define MT_DEVICE_WC 3 /* * types 4 onwards can be found in asm/mach/map.h and are undefined * for ioremap */ /* * __arm_ioremap takes CPU physical address. * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page * The _caller variety takes a __builtin_return_address(0) value for * /proc/vmalloc to use - and should only be used in non-inline functions. */ extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long, size_t, unsigned int, void *); extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int, void *); extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int); extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached); extern void __iounmap(volatile void __iomem *addr); extern void __arm_iounmap(volatile void __iomem *addr); extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *); extern void (*arch_iounmap)(volatile void __iomem *); /* * Bad read/write accesses... */ extern void __readwrite_bug(const char *fn); /* * A typesafe __io() helper */ static inline void __iomem *__typesafe_io(unsigned long addr) { return (void __iomem *)addr; } #define IOMEM(x) ((void __force __iomem *)(x)) /* IO barriers */ #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE #include #define __iormb() rmb() #define __iowmb() wmb() #else #define __iormb() do { } while (0) #define __iowmb() do { } while (0) #endif /* PCI fixed i/o mapping */ #define PCI_IO_VIRT_BASE 0xfee00000 extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); /* * Now, pick up the machine-defined IO definitions */ #ifdef CONFIG_NEED_MACH_IO_H #include #elif defined(CONFIG_PCI) #define IO_SPACE_LIMIT ((resource_size_t)0xfffff) #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) #else #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) #endif /* * This is the limit of PC card/PCI/ISA IO space, which is by default * 64K if we have PC card, PCI or ISA support. Otherwise, default to * zero to prevent ISA/PCI drivers claiming IO space (and potentially * oopsing.) * * Only set this larger if you really need inb() et.al. to operate over * a larger address space. Note that SOC_COMMON ioremaps each sockets * IO space area, and so inb() et.al. must be defined to operate as per * readb() et.al. on such platforms. */ #ifndef IO_SPACE_LIMIT #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE) #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff) #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD) #define IO_SPACE_LIMIT ((resource_size_t)0xffff) #else #define IO_SPACE_LIMIT ((resource_size_t)0) #endif #endif /* * IO port access primitives * ------------------------- * * The ARM doesn't have special IO access instructions; all IO is memory * mapped. Note that these are defined to perform little endian accesses * only. Their primary purpose is to access PCI and ISA peripherals. * * Note that for a big endian machine, this implies that the following * big endian mode connectivity is in place, as described by numerous * ARM documents: * * PCI: D0-D7 D8-D15 D16-D23 D24-D31 * ARM: D24-D31 D16-D23 D8-D15 D0-D7 * * The machine specific io.h include defines __io to translate an "IO" * address to a memory address. * * Note that we prevent GCC re-ordering or caching values in expressions * by introducing sequence points into the in*() definitions. Note that * __raw_* do not guarantee this behaviour. *