/*
 * Copyright 2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 */

#ifndef __MACH_BOARD_CNS3XXXH
#define __MACH_BOARD_CNS3XXXH

/*
 * Memory map
 */
#define CNS3XXX_FLASH_BASE			0x10000000	/* Flash/SRAM Memory Bank 0 */
#define CNS3XXX_FLASH_SIZE			SZ_256M

#define CNS3XXX_DDR2SDRAM_BASE			0x20000000	/* DDR2 SDRAM Memory */

#define CNS3XXX_SPI_FLASH_BASE			0x60000000	/* SPI Serial Flash Memory */

#define CNS3XXX_SWITCH_BASE			0x70000000	/* Switch and HNAT Control */
#define CNS3XXX_SWITCH_BASE_VIRT		0xFFF00000

#define CNS3XXX_PPE_BASE			0x70001000	/* HANT	*/
#define CNS3XXX_PPE_BASE_VIRT			0xFFF50000

#define CNS3XXX_EMBEDDED_SRAM_BASE		0x70002000	/* HANT Embedded SRAM */
#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT		0xFFF60000

#define CNS3XXX_SSP_BASE			0x71000000	/* Synchronous Serial Port - SPI/PCM/I2C */
#define CNS3XXX_SSP_BASE_VIRT			0xFFF01000

#define CNS3XXX_DMC_BASE			0x72000000	/* DMC Control (DDR2 SDRAM) */
#define CNS3XXX_DMC_BASE_VIRT			0xFFF02000

#define CNS3XXX_SMC_BASE			0x73000000	/* SMC Control */
#define CNS3XXX_SMC_BASE_VIRT			0xFFF03000

#define SMC_MEMC_STATUS_OFFSET			0x000
#define SMC_MEMIF_CFG_OFFSET			0x004
#define SMC_MEMC_CFG_SET_OFFSET			0x008
#define SMC_MEMC_CFG_CLR_OFFSET			0x00C
#define SMC_DIRECT_CMD_OFFSET			0x010
#define SMC_SET_CYCLES_OFFSET			0x014
#define SMC_SET_OPMODE_OFFSET			0x018
#define SMC_REFRESH_PERIOD_0_OFFSET		0x020
#define SMC_REFRESH_PERIOD_1_OFFSET		0x024
#define SMC_SRAM_CYCLES0_0_OFFSET		0x100
#define SMC_NAND_CYCLES0_0_OFFSET		0x100
#define SMC_OPMODE0_0_OFFSET			0x104
#define SMC_SRAM_CYCLES0_1_OFFSET		0x120
#define SMC_NAND_CYCLES0_1_OFFSET		0x120
#define SMC_OPMODE0_1_OFFSET			0x124
#define SMC_USER_STATUS_OFFSET			0x200
#define SMC_USER_CONFIG_OFFSET			0x204
#define SMC_ECC_STATUS_OFFSET			0x300
#define SMC_ECC_MEMCFG_OFFSET			0x304
#define SMC_ECC_MEMCOMMAND1_OFFSET		0x308
#define SMC_ECC_MEMCOMMAND2_OFFSET		0x30C
#define SMC_ECC_ADDR0_OFFSET			0x310
#define SMC_ECC_ADDR1_OFFSET			0x314
#define SMC_ECC_VALUE0_OFFSET			0x318
#define SMC_ECC_VALUE1_OFFSET			0x31C
#define SMC_ECC_VALUE2_OFFSET			0x320
#define SMC_ECC_VALUE3_OFFSET			0x324
#define SMC_PERIPH_ID_0_OFFSET			0xFE0
#define SMC_PERIPH_ID_1_OFFSET			0xFE4
#define SMC_PERIPH_ID_2_OFFSET			0xFE8
#define SMC_PERIPH_ID_3_OFFSET			0xFEC
#define SMC_PCELL_ID_0_OFFSET			0xFF0
#define SMC_PCELL_ID_1_OFFSET			0xFF4
#define SMC_PCELL_ID_2_OFFSET			0xFF8
#define SMC_PCELL_ID_3_OFFSET			0xFFC

#define CNS3XXX_GPIOA_BASE			0x74000000	/* GPIO port A */
#define CNS3XXX_GPIOA_BASE_VIRT			0xFFF04000

#define CNS3XXX_GPIOB_BASE			0x74800000	/* GPIO port B */
#define CNS3XXX_GPIOB_BASE_VIRT			0xFFF05000

#define CNS3XXX_RTC_BASE			0x75000000	/* Real Time Clock */
#define CNS3XXX_RTC_BASE_VIRT			0xFFF06000

#define RTC_SEC_OFFSET				0x00
#define RTC_MIN_OFFSET				0x04
#define RTC_HOUR_OFFSET				0x08
#define RTC_DAY_OFFSET				0x0C
#define RTC_SEC_ALM_OFFSET			0x10
#define RTC_MIN_ALM_OFFSET			0x14
#define RTC_HOUR_ALM_OFFSET			0x18
#define RTC_REC_OFFSET				0x1C
#define RTC_CTRL_OFFSET				0x20
#define RTC_INTR_STS_OFFSET			0x34

#define CNS3XXX_MISC_BASE			0x76000000	/* Misc Control */
#define CNS3XXX_MISC_BASE_VIRT			0xFB000000	/* Misc Control */

#define CNS3XXX_PM_BASE				0x77000000	/* Power Management Control */
#define CNS3XXX_PM_BASE_VIRT			0xFB001000

#define PM_CLK_GATE_OFFSET			0x00
#define PM_SOFT_RST_OFFSET			0x04
#define PM_HS_CFG_OFFSET			0x08
#define PM_CACTIVE_STA_OFFSET			0x0C
#define PM_PWR_STA_OFFSET			0x10
#define PM_SYS_CLK_CTRL_OFFSET			0x14
#define PM_PLL_LCD_I2S_CTRL_OFFSET		0x18
#define PM_PLL_HM_PD_OFFSET			0x1C

#define CNS3XXX_UART0_BASE			0x78000000	/* UART 0 */
#define CNS3XXX_UART0_BASE_VIRT			0xFB002000

#define CNS3XXX_UART1_BASE			0x78400000	/* UART 1 */
#define CNS3XXX_UART1_BASE_VIRT			0xFFF0A000

#define CNS3XXX_UART2_BASE			0x78800000	/* UART 2 */
#define CNS3XXX_UART2_BASE_VIRT			0xFFF0B000

#define CNS3XXX_DMAC_BASE			0x79000000	/* Generic DMA Control */
#define CNS3XXX_DMAC_BASE_VIRT			0xFFF0D000

#define CNS3XXX_CORESIGHT_BASE			0x7A000000	/* CoreSight */
#define CNS3XXX_CORESIGHT_BASE_VIRT		0xFFF0E000

#define CNS3XXX_CRYPTO_BASE			0x7B000000	/* Crypto */
#define CNS3XXX_CRYPTO_BASE_VIRT		0xFFF0F000

#define CNS3XXX_I2S_BASE			0x7C000000	/* I2S */
#define CNS3XXX_I2S_BASE_VIRT			0xFFF10000

#define CNS3XXX_TIMER1_2_3_BASE			0x7C800000	/* Timer */
#define CNS3XXX_TIMER1_2_3_BASE_VIRT		0xFB003000

#define TIMER1_COUNTER_OFFSET			0x00
#define TIMER1_AUTO_RELOAD_OFFSET		0x04
#define TIMER1_MATCH_V1_OFFSET			0x08
#define TIMER1_MATCH_V2_OFFSET			0x0C

#define TIMER2_COUNTER_OFFSET			0x10
#define TIMER2_AUTO_RELOAD_OFFSET		0x14
#define TIMER2_MATCH_V1_OFFSET			0x18
#define TIMER2_MATCH_V2_OFFSET			0x1C

#define TIMER1_2_CONTROL_OFFSET			0x30
#define TIMER1_2_INTERRUPT_STATUS_OFFSET	0x34
#define TIMER1_2_INTERRUPT_MASK_OFFSET		0x38

#define TIMER_FREERUN_OFFSET			0x40
#define TIMER_FREERUN_CONTROL_OFFSET		0x44

#define CNS3XXX_HCIE_BASE			0x7D000000	/* HCIE Control */
#define CNS3XXX_HCIE_BASE_VIRT			0xFFF30000

#define CNS3XXX_RAID_BASE			0x7E000000	/* RAID Control */
#define CNS3XXX_RAID_BASE_VIRT			0xFFF12000

#define CNS3XXX_AXI_IXC_BASE			0x7F000000	/* AXI IXC */
#define CNS3XXX_AXI_IXC_BASE_VIRT		0xFFF13000

#define CNS3XXX_CLCD_BASE			0x80000000	/* LCD Control */
#define CNS3XXX_CLCD_BASE_VIRT			0xFFF14000

#define CNS3XXX_USBOTG_BASE			0x81000000	/* USB OTG Control */
#define CNS3XXX_USBOTG_BASE_VIRT		0xFFF15000

#define CNS3XXX_USB_BASE			0x82000000	/* USB Host Control */

#define CNS3XXX_SATA2_BASE			0x83000000	/* SATA */
#define CNS3XXX_SATA2_SIZE			SZ_16M
#define CNS3XXX_SATA2_BASE_VIRT			0xFFF17000

#define CNS3XXX_CAMERA_BASE			0x84000000	/* Camera Interface */
#define CNS3XXX_CAMERA_BASE_VIRT		0xFFF18000

#define CNS3XXX_SDIO_BASE			0x85000000	/* SDIO */
#define CNS3XXX_SDIO_BASE_VIRT			0xFFF19000

#define CNS3XXX_I2S_TDM_BASE			0x86000000	/* I2S TDM */
#define CNS3XXX_I2S_TDM_BASE_VIRT		0xFFF1A000

#define CNS3XXX_2DG_BASE			0x87000000	/* 2D Graphic Control */
#define CNS3XXX_2DG_BASE_VIRT			0xFFF1B000

#define CNS3XXX_USB_OHCI_BASE			0x88000000	/* USB OHCI */

#define CNS3XXX_L2C_BASE			0x92000000	/* L2 Cache Control */
#define CNS3XXX_L2C_BASE_VIRT			0xFFF27000

#define CNS3XXX_PCIE0_MEM_BASE			0xA0000000	/* PCIe Port 0 IO/Memory Space */
#define CNS3XXX_PCIE0_MEM_BASE_VIRT		0xE0000000

#define CNS3XXX_PCIE0_HOST_BASE			0xAB000000	/* PCIe Port 0 RC Base */
#define CNS3XXX_PCIE0_HOST_BASE_VIRT		0xE1000000

#define CNS3XXX_PCIE0_IO_BASE			0xAC000000	/* PCIe Port 0 */
#define CNS3XXX_PCIE0_IO_BASE_VIRT		0xE2000000