/* linux/arch/arm/plat-s3c24xx/irq.c * * Copyright (c) 2003-2004 Simtec Electronics * Ben Dooks * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include #include #include #include #include #include #include #include #include #include #include #include static void s3c_irq_mask(struct irq_data *data) { unsigned int irqno = data->irq - IRQ_EINT0; unsigned long mask; mask = __raw_readl(S3C2410_INTMSK); mask |= 1UL << irqno; __raw_writel(mask, S3C2410_INTMSK); } static inline void s3c_irq_ack(struct irq_data *data) { unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); __raw_writel(bitval, S3C2410_SRCPND); __raw_writel(bitval, S3C2410_INTPND); } static inline void s3c_irq_maskack(struct irq_data *data) { unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); unsigned long mask; mask = __raw_readl(S3C2410_INTMSK); __raw_writel(mask|bitval, S3C2410_INTMSK); __raw_writel(bitval, S3C2410_SRCPND); __raw_writel(bitval, S3C2410_INTPND); } static void s3c_irq_unmask(struct irq_data *data) { unsigned int irqno = data->irq; unsigned long mask; if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23) irqdbf2("s3c_irq_unmask %d\n", irqno); irqno -= IRQ_EINT0; mask = __raw_readl(S3C2410_INTMSK); mask &= ~(1UL << irqno); __raw_writel(mask, S3C2410_INTMSK); } struct irq_chip s3c_irq_level_chip = { .name = "s3c-level", .irq_ack = s3c_irq_maskack, .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, .irq_set_wake = s3c_irq_wake }; struct irq_chip s3c_irq_chip = { .name = "s3c", .irq_ack = s3c_irq_ack, .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, .irq_set_wake = s3c_irq_wake }; static void s3c_irqext_mask(struct irq_data *data) { unsigned int irqno = data->irq - EXTINT_OFF; unsigned long mask; mask = __raw_readl(S3C24XX_EINTMASK); mask |= ( 1UL << irqno); __raw_writel(mask, S3C24XX_EINTMASK); } static void s3c_irqext_ack(struct irq_data *data) { unsigned long req; unsigned long bit; unsigned long mask; bit = 1UL << (data->irq - EXTINT_OFF); mask = __raw_readl(S3C24XX_EINTMASK); __raw_writel(bit, S3C24XX_EINTPEND); req = __raw_readl(S3C24XX_EINTPEND); req &= ~mask; /* not sure if we should be acking the parent irq... */ if (data->irq <= IRQ_EINT7) { if ((req & 0xf0) == 0) s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7)); } else { if ((req >> 8) == 0) s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23)); } } static void s3c_irqext_unmask(struct irq_data *data) { unsigned int irqno = data->irq - EXTINT_OFF; unsigned long mask; mask = __raw_readl(S3C24XX_EINTMASK); mask &= ~(1UL << irqno); __raw_writel(mask, S3C24XX_EINTMASK); } int s3c_irqext_type(struct irq_data *data, unsigned int type) { void __iomem *extint_reg; void __iomem *gpcon_reg; unsigned long gpcon_offset, extint_offset; unsigned long newvalue = 0, value; if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) { gpcon_reg = S3C2410_GPFCON; extint_reg = S3C24XX_EXTINT0; gpcon_offset = (data->irq - IRQ_EINT0) * 2; extint_offset = (data->irq - IRQ_EINT0) * 4; } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) { gpcon_reg = S3C2410_GPFCON; extint_reg = S3C24XX_EXTINT0; gpcon_offset = (data->irq - (EXTINT_OFF)) * 2; extint_offset = (data->irq - (EXTINT_OFF)) * 4; } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) { gpcon_reg = S3C2410_GPGCON; extint_reg = S3C24XX_EXTINT1; gpcon_offset = (data->irq - IRQ_EINT8) * 2; extint_offset = (data->irq - IRQ_EINT8) * 4; } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) { gpcon_reg = S3C2410_GPGCON; extint_reg = S3C24XX_EXTINT2; gpcon_offset = (data->irq - IRQ_EINT8) * 2; extint_offset = (data->irq - IRQ_EINT16) * 4; } else { return -1; } /* Set the GPIO to external interrupt mode */ value = __raw_readl(gpcon_reg); value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); __raw_writel(value, gpcon_reg); /* Set the external interrupt to pointed trigger type */ switch (type) { case IRQ_TYPE_NONE: printk(KERN_WARNING "No edge setting!\n"); break; case IRQ_TYPE_EDGE_RISING: newvalue = S3C2410_EXTINT_RISEEDGE; break; case IRQ_TYPE_EDGE_FALLING: newvalue = S3C2410_EXTINT_FALLEDGE; break; case IRQ_TYPE_EDGE_BOTH: newvalue = S3C2410_EXTINT_BOTHEDGE; break; case IRQ_TYPE_LEVEL_LOW: newvalue = S3C2410_EXTINT_LOWLEV; break; case IRQ_TYPE_LEVEL_HIGH: newvalue = S3C2410_EXTINT_HILEV; break; default: printk(KERN_ERR "No such irq type %d", type); return -1; } value = __raw_readl(extint_reg); value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); __raw_writel(value, extint_reg); return 0; } static struct irq_chip s3c_irqext_chip = { .name = "s3c-ext", .irq_mask = s3c_irqext_mask, .irq_unmask = s3c_irqext_unmask, .irq_ack = s3c_irqext_ack, .irq_set_type = s3c_irqext_type, .irq_set_wake = s3c_irqext_wake }; static struct irq_chip s3c_irq_eint0t4 = { .name = "s3c-ext0", .irq_ack = s3c_irq_ack, .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, .irq_set_wake = s3c_irq_wake, .irq_set_type = s3c_irqext_type, }; /* mask values for the parent registers for each of the interrupt types */ #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0)) #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0)) #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0)) #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0)) /* UART0 */ static void s3c_irq_uart0_mask(struct irq_data *data) { s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);