/* * FILE SA-1100.h * * Version 1.2 * Author Copyright (c) Marc A. Viredaz, 1998 * DEC Western Research Laboratory, Palo Alto, CA * Date January 1998 (April 1997) * System StrongARM SA-1100 * Language C or ARM Assembly * Purpose Definition of constants related to the StrongARM * SA-1100 microprocessor (Advanced RISC Machine (ARM) * architecture version 4). This file is based on the * StrongARM SA-1100 data sheet version 2.2. * */ /* Be sure that virtual mapping is defined right */ #ifndef __ASM_ARCH_HARDWARE_H #error You must include hardware.h not SA-1100.h #endif #include "bitfield.h" /* * SA1100 CS line to physical address */ #define SA1100_CS0_PHYS 0x00000000 #define SA1100_CS1_PHYS 0x08000000 #define SA1100_CS2_PHYS 0x10000000 #define SA1100_CS3_PHYS 0x18000000 #define SA1100_CS4_PHYS 0x40000000 #define SA1100_CS5_PHYS 0x48000000 /* * Personal Computer Memory Card International Association (PCMCIA) sockets */ #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ (0x20000000 + (Nb)*PCMCIASp) #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ (_PCMCIA (Nb) + 2*PCMCIAPrtSp) #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ (_PCMCIA (Nb) + 3*PCMCIAPrtSp) #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ /* * Universal Serial Bus (USB) Device Controller (UDC) control registers * * Registers * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control Register (read/write). * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Address Register (read/write). * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Output Maximum Packet size register * (read/write). * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Input Maximum Packet size register * (read/write). * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 0 * (read/write). * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 1 * (output, read/write). * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 2 * (input, read/write). * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Data register end-point 0 * (read/write). * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Write Count register end-point 0 * (read). * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Data Register (read/write). * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Status Register (read/write). */ #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ #define UDCCR_UDD 0x00000001 /* UDC Disable */ #define UDCCR_UDA 0x00000002 /* UDC Active (read) */ #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ /* (disable) */ #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ /* (disable) */ #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ /* (disable) */ #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ /* (disable) */ #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ #define UDCAR_ADD Fld (7, 0) /* function ADDress */ #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ /* [byte] */ #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ /* [byte] */ #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCIMP_INMAXP)) #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ #define UDCCS0_SST 0x00000004 /* Sent STall */ #define UDCCS0_FST 0x00000008 /* Force STall */ #define UDCCS0_DE 0x00000010 /* Data End */ #define UDCCS0_SE 0x00000020 /* Setup End (read) */ #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ /* (write) */ #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ /* Service request (read) */ #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ #define UDCCS1_SST 0x00000008 /* Sent STall */ #define UDCCS1_FST 0x00000010 /* Force STall */ #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ /* Service request (read) */ #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */