/* * linux/arch/arm/mach-omap2/clock.h * * Copyright (C) 2005-2009 Texas Instruments, Inc. * Copyright (C) 2004-2011 Nokia Corporation * * Contacts: * Richard Woodruff * Paul Walmsley * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H #define __ARCH_ARM_MACH_OMAP2_CLOCK_H #include #include #include #include struct omap_clk { u16 cpu; struct clk_lookup lk; }; #define CLK(dev, con, ck, cp) \ { \ .cpu = cp, \ .lk = { \ .dev_id = dev, \ .con_id = con, \ .clk = ck, \ }, \ } /* Platform flags for the clkdev-OMAP integration code */ #define CK_242X (1 << 0) #define CK_243X (1 << 1) /* 243x, 253x */ #define CK_3430ES1 (1 << 2) /* 34xxES1 only */ #define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */ #define CK_AM35XX (1 << 4) /* Sitara AM35xx */ #define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */ #define CK_443X (1 << 6) #define CK_TI816X (1 << 7) #define CK_446X (1 << 8) #define CK_AM33XX (1 << 9) /* AM33xx specific clocks */ #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) struct clockdomain; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ static struct clk _name = { \ .name = #_name, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_array_name, \ .num_parents = ARRAY_SIZE(_parent_array_name), \ .ops = &_clkops_name, \ }; #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .clkdm_name = _clkdm_name, \ }; #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ _clksel_reg, _clksel_mask, \ _parent_names, _ops) \ static struct clk _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .clksel = _clksel, \ .clksel_reg = _clksel_reg, \ .clksel_mask = _clksel_mask, \ .clkdm_name = _clkdm_name, \ }; \ DEFINE_STRUCT_CLK(_name, _parent_names, _ops); #define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ _clksel_reg, _clksel_mask, \ _enable_reg, _enable_bit, \ _hwops, _parent_names, _ops) \ static struct clk _name; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .ops = _hwops, \ .enable_reg = _enable_reg, \ .enable_bit = _enable_bit, \ .clksel = _clksel, \ .clksel_reg = _clksel_reg, \ .clksel_mask = _clksel_mask, \ .clkdm_name = _clkdm_name, \ }; \ DEFINE_STRUCT_CLK(_name, _parent_names, _ops); #define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ _parent_ptr, _flags, \ _clksel_reg, _clksel_mask) \ static const struct clksel _name##_div[] = { \ { \ .parent = _parent_ptr, \ .rates = div31_1to31_rates \ }, \ { .parent = NULL }, \ }; \ static struct clk _name; \ static const char *_name##_parent_names[] = { \ _parent_name, \ }; \ static struct clk_hw_omap _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .clksel = _name##_div, \ .clksel_reg = _clksel_reg, \ .clksel_mask = _clksel_mask, \ .ops = &clkhwops_omap4_dpllmx, \ }; \ DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ #define RATE_IN_36XX (1 << 4) #define RATE_IN_4430 (1 << 5) #define RATE_IN_TI816X (1 << 6) #define RATE_IN_4460 (1 << 7) #define RATE_IN_AM33XX (1 << 8) #define RATE_IN_TI814X (1 << 9) #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) /** * struct clksel_rate - register bitfield values corresponding to clk divisors * @val: register bitfield value (shifted to bit 0) * @div: clock divisor corresponding to @val * @flags: (see "struct clksel_rate.flags possibilities" above) * * @val should match the value of a read from struct clk.clksel_reg * AND'ed with struct clk.clksel_mask, shifted right to bit 0. * * @div is the divisor that should be applied to the parent clock's rate * to produce the current clock's rate. */ struct clksel_rate { u32 val; u8 div; u16 flags; }; /** * struct clksel - available parent clocks, and a pointer to their divisors * @parent: struct clk * to a possible parent clock * @rates: available divisors for this parent clock * * A struct clksel is always associated with one or more struct clks * and one or more struct clksel_rates. */ struct clksel { struct clk *parent; const struct clksel_rate *rates; }; /** * struct dpll_data - DPLL registers and integration data * @mult_div1_reg: register containing the DPLL M and N bitfields * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg * @clk_bypass: struct clk pointer to the clock's bypass clock input * @clk_ref: struct clk pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() * @last_rounded_m4xen: cache of the last M4X result of * omap4_dpll_regm4xen_round_rate() * @last_rounded_lpmode: cache of the last lpmode result of * omap4_dpll_lpmode_recalc() * @max_multiplier: maximum valid non-bypass multiplier value (actual) * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() * @min_divider: minimum valid non-bypass divider value (actual) * @max_divider: maximum valid non-bypass divider value (actual) * @modes: possible values of @enable_mask * @autoidle_reg: register containing the DPLL autoidle mode bitfield * @idlest_reg: register containing the DPLL idle status bitfield * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs * @flags: DPLL type/features (see below) * * Possible values for @flags: * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) * * @freqsel_mask is only used on the OMAP34xx family and AM35xx. * * XXX Some DPLLs have multiple bypass inputs, so it's not technically * correct to only have one @clk_bypass pointer. * * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, * @last_rounded_n) should be separated from the runtime-fixed fields * and placed into a different structure, so that the runtime-fixed data * can be placed into read-only space. */ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; struct clk *clk_bypass; struct clk *clk_ref; void __iomem *control_reg; u32 enable_mask; unsigned long last_rounded_rate; u16 last_rounded_m; u8 last_rounded_m4xen; u8 last_rounded_lpmode; u16 max_multiplier; u8 last_rounded_n; u8 min_divider; u16 max_divider; u8 modes; void __iomem *autoidle_reg; void __iomem *idlest_reg; u32 autoidle_mask; u32 freqsel_mask; u32 idlest_mask; u32 dco_mask; u32 sddiv_mask; u32 lpmode_mask; u32 m4xen_mask; u8 auto_recal_bit; u8 recal_en_bit; u8 recal_st_bit; u8 flags; }; /* * struct clk.flags possibilities * * XXX document the rest of the clock flags here * * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL * bits share the same register. This flag allows the * omap4_dpllmx*() code to determine which GATE_CTRL bit field * should be used. This is a temporary solution - a better approach * would be to associate clock type-specific data with the clock, * similar to the struct dpll_data approach. */ #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ #define CLOCK_IDLE_CONTROL (1 << 1) #define CLOCK_NO_IDLE_PARENT (1 << 2) #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ #define CLOCK_CLKOUTX2 (1 << 5) /** * struct clk_hw_omap - OMAP struct clk * @node: list_head connecting this clock into the full clock list * @enable_reg: register to write to enable the clock (see @enable_bit) * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) * @flags: see "struct clk.flags possibilities" above * @clksel_reg: for clksel clks, register va containing src/divisor select * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector * @clksel: for clksel clks, pointer to struct clksel for this clock * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock * @clkdm_name: clockdomain name that this clock is contained in * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) * @src_offset: bitshift for source selection bitfield (OMAP1 only) * * XXX @rate_offset, @src_offset should probably be removed and OMAP1 * clock code converted to use clksel. * */ struct clk_hw_omap_ops; struct clk_hw_omap { struct clk_hw hw; struct list_head node; unsigned long fixed_rate; u8 fixed_div; void __iomem *enable_reg; u8 enable_bit; u8 flags; void __iomem *clksel_reg; u32 clksel_mask; const struct clksel *clksel; struct dpll_data *dpll_data; const char *clkdm_name; struct clockdomain *clkdm;