/* * SH7372 clock framework support * * Copyright (C) 2010 Magnus Damm * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include #include #include #include #include #include /* SH7372 registers */ #define FRQCRA IOMEM(0xe6150000) #define FRQCRB IOMEM(0xe6150004) #define FRQCRC IOMEM(0xe61500e0) #define FRQCRD IOMEM(0xe61500e4) #define VCLKCR1 IOMEM(0xe6150008) #define VCLKCR2 IOMEM(0xe615000c) #define VCLKCR3 IOMEM(0xe615001c) #define FMSICKCR IOMEM(0xe6150010) #define FMSOCKCR IOMEM(0xe6150014) #define FSIACKCR IOMEM(0xe6150018) #define FSIBCKCR IOMEM(0xe6150090) #define SUBCKCR IOMEM(0xe6150080) #define SPUCKCR IOMEM(0xe6150084) #define VOUCKCR IOMEM(0xe6150088) #define HDMICKCR IOMEM(0xe6150094) #define DSITCKCR IOMEM(0xe6150060) #define DSI0PCKCR IOMEM(0xe6150064) #define DSI1PCKCR IOMEM(0xe6150098) #define PLLC01CR IOMEM(0xe6150028) #define PLLC2CR IOMEM(0xe615002c) #define RMSTPCR0 IOMEM(0xe6150110) #define RMSTPCR1 IOMEM(0xe6150114) #define RMSTPCR2 IOMEM(0xe6150118) #define RMSTPCR3 IOMEM(0xe615011c) #define RMSTPCR4 IOMEM(0xe6150120) #define SMSTPCR0 IOMEM(0xe6150130) #define SMSTPCR1 IOMEM(0xe6150134) #define SMSTPCR2 IOMEM(0xe6150138) #define SMSTPCR3 IOMEM(0xe615013c) #define SMSTPCR4 IOMEM(0xe6150140) #define FSIDIVA 0xFE1F8000 #define FSIDIVB 0xFE1F8008 /* Platforms must set frequency on their DV_CLKI pin */ struct clk sh7372_dv_clki_clk = { }; /* Fixed 32 KHz root clock from EXTALR pin */ static struct clk r_clk = { .rate = 32768, }; /* * 26MHz default rate for the EXTAL1 root input clock. * If needed, reset this with clk_set_rate() from the platform code. */ struct clk sh7372_extal1_clk = { .rate = 26000000, }; /* * 48MHz default rate for the EXTAL2 root input clock. * If needed, reset this with clk_set_rate() from the platform code. */ struct clk sh7372_extal2_clk = { .rate = 48000000, }; /* A fixed divide-by-2 block */ static unsigned long div2_recalc(struct clk *clk) { return clk->parent->rate / 2; } static struct sh_clk_ops div2_clk_ops = { .recalc = div2_recalc, }; /* Divide dv_clki by two */ struct clk sh7372_dv_clki_div2_clk = { .ops = &div2_clk_ops, .parent = &sh7372_dv_clki_clk, }; /* Divide extal1 by two */ static struct clk extal1_div2_clk = { .ops = &div2_clk_ops, .parent = &sh7372_extal1_clk, }; /* Divide extal2 by two */ static struct clk extal2_div2_clk = { .ops = &div2_clk_ops, .parent = &sh7372_extal2_clk, }; /* Divide extal2 by four */ static struct clk extal2_div4_clk = { .ops = &div2_clk_ops, .parent = &extal2_div2_clk, }; /* PLLC0 and PLLC1 */ static unsigned long pllc01_recalc(struct clk *clk) { unsigned long mult = 1; if (__raw_readl(PLLC01CR) & (1 << 14)) mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2; return clk->parent->rate * mult; } static struct sh_clk_ops pllc01_clk_ops = { .recalc = pllc01_recalc, }; static struct clk pllc0_clk = { .ops = &pllc01_clk_ops, .flags = CLK_ENABLE_ON_INIT, .parent = &extal1_div2_clk, .enable_reg = (void __iomem *)FRQCRC, }; static struct clk pllc1_clk = { .ops = &pllc01_clk_ops, .flags = CLK_ENABLE_ON_INIT, .parent = &extal1_div2_clk, .enable_reg = (void __iomem *)FRQCRA, }; /* Divide PLLC1 by two */ static struct clk pllc1_div2_clk = { .ops = &div2_clk_ops, .parent = &pllc1_clk, }; /* PLLC2 */ /* Indices are important - they are the actual src selecting values */ static struct clk *pllc2_parent[] = { [0] = &extal1_div2_clk, [1] = &extal2_div2_clk, [2] = &sh7372_dv_clki_div2_clk, }; /* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */ static struct cpufreq_frequency_table pllc2_freq_table[29]; static void pllc2_table_rebuild(struct clk *clk) { int i; /* Initialise PLLC2 frequency table */ for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) { pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2; pllc2_freq_table[i].index = i; } /* This is a special entry - switching PLL off makes it a repeater */ pllc2_freq_table[i].frequency = clk->parent->rate; pllc2_freq_table[i].index = i; pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END; pllc2_freq_table[i].index = i; } static unsigned long pllc2_recalc(struct clk *clk) { unsigned long mult = 1; pllc2_table_rebuild(clk); /* * If the PLL is off, mult == 1, clk->rate will be updated in * pllc2_enable(). */ if (__raw_readl(PLLC2CR) & (1 << 31)) mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2; return clk->parent->rate * mult; } static long pllc2_round_rate(struct clk *clk, unsigned long rate) { return clk_rate_table_round(clk, clk->freq_table, rate); } static int pllc2_enable(struct clk *clk) { int i; __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR); for (i = 0; i < 100; i++) if (__raw_readl(PLLC2CR) & 0x80000000) { clk->rate = pllc2_recalc(clk); return 0; } pr_err("%s(): timeout!\n", __func__); return -ETIMEDOUT; } static void pllc2_disable(struct clk *clk) { __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR); } static int pllc2_set_rate(struct clk *clk, unsigned long rate) { unsigned long value; int idx; idx = clk_rate_table_find(clk, clk->freq_table, rate); if (idx < 0) return idx; if (rate == clk->parent->rate) return -EINVAL; value = __raw_readl(PLLC2CR) & ~(0x3f << 24); __raw_writel(value | ((idx + 19) << 24), PLLC2CR); clk->rate = clk->freq_table[idx].frequency; return 0; } static int pllc2_set_parent(struct clk *clk, struct clk *parent) { u32 value; int ret, i; if (!clk->parent_table || !clk->parent_num) return -EINVAL; /* Search the parent */ for (i = 0; i < clk->parent_num; i++) if (clk->parent_table[i] == parent) break; if (i == clk->parent_num) return -ENODEV; ret = clk_reparent(clk, parent); if (ret < 0) return ret; value = __raw_readl(PLLC2CR) & ~(3 << 6); __raw_writel(value | (i << 6), PLLC2CR); /* Rebiuld the frequency table */ pllc2_table_rebuild(clk); return 0; } static struct sh_clk_ops pllc2_clk_ops = { .recalc = pllc2_recalc, .round_rate = pllc2_round_rate, .set_rate = pllc2_set_rate, .enable = pllc2_enable, .disable = pllc2_disable, .set_parent = pllc2_set_parent, }; struct clk sh7372_pllc2_clk = { .ops = &pllc2_clk_ops, .parent = &extal1_div2_clk, .freq_table = pllc2_freq_table, .nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1, .parent_table = pllc2_parent, .parent_num = ARRAY_SIZE(pllc2_parent), }; /* External input clock (pin name: FSIACK/FSIBCK ) */ static struct clk fsiack_clk = { }; static struct clk fsibck_clk = { }; static struct clk *main_clks[] = { &sh7372_dv_clki_clk, &r_clk, &sh7372_extal1_clk, &sh7372_extal2_clk, &sh7372_dv_clki_div2_clk, &extal1_div2_clk, &extal2_div2_clk, &extal2_div4_clk, &pllc0_clk, &pllc1_clk, &pllc1_div2_clk, &sh7372_pllc2_clk, &fsiack_clk, &fsibck_clk, }; static void div4_kick(struct clk *clk) { unsigned long value; /* set KICK bit in FRQCRB to update hardware setting */ value = __raw_readl(FRQCRB); value |= (1 << 31); __raw_writel(value, FRQCRB); } static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 32, 36, 48, 0, 72, 96, 0 }; static struct clk_div_mult_table div4_div_mult_table = { .divisors = divisors, .nr_divisors = ARRAY_SIZE(divisors), }; static struct clk_div4_table div4_table = { .div_mult_table = &div4_div_mult_table, .kick = div4_kick, }; enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_DDRP, DIV4_NR }; #define DIV4(_reg, _bit, _mask, _flags) \ SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags) static struct clk div4_clks[DIV4_NR] = { [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0), [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0), [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0), [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0), [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0), [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0), }; enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO, DIV6_SUB, DIV6_SPU, DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, DIV6_NR }; static struct clk div6_clks[DIV6_NR] = { [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0), [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0), [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0), [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0), [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0), [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0), [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0), [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0), [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0), [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0), [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0), }; enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR }; /* Indices are important - they are the actual src selecting values */ static struct clk *hdmi_parent[] = { [0] = &pllc1_div2_clk, [1] = &sh7372_pllc2_clk, [2] = &sh7372_dv_clki_clk, [3] = NULL, /* pllc2_div4 not implemented yet */ }; static struct clk *fsiackcr_parent[] = { [0] = &pllc1_div2_clk, [1] = &sh7372_pllc2_clk, [2] = &fsiack_clk, /* external input for FSI A */ [3] = NULL, /* setting prohibited */ }; static struct clk *fsibckcr_parent[] = { [0] = &pllc1_div2_clk, [1] = &sh7372_pllc2_clk, [2] = &fsibck_clk, /* external input for FSI B */ [3] = NULL, /* setting prohibited */ };